ahb: backport bridge to chisel2

Closes #47
2016-05-25 12:25:59 -07:00 · 2016-05-25 12:25:59 -07:00 · 7f1792cba3
commit 7f1792cba3
parent c49cb10c74
1 changed files with 1 additions and 1 deletions
--- a/uncore/src/main/scala/ahb.scala
+++ b/uncore/src/main/scala/ahb.scala
@ -241,7 +241,7 @@ class AHBBusMaster(implicit val p: Parameters) extends Module
  val hmastlock = Reg(init = Bool(false))
  val hwrite    = Reg(Bool())
  val hburst    = Reg(UInt())
-  val hsize     = Reg(UInt())
+  val hsize     = Reg(init = UInt(0, width = SZ_HSIZE))
  val hprot     = Reg(UInt())
  val hwdata0   = Reg(Bits())
  val hwdata1   = Reg(Bits())