riscv/rocket-chip
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Don't stall I$ response when resolving a branch misprediction

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This avoids a fetch bubble.

Not clear if this is the best way to do it.  Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
This commit is contained in:
Andrew Waterman 2016-05-22 14:08:53 -07:00
parent d7790ac6a4
commit 354cb2d5ec
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/rocket.scala
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@ -505,7 +505,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
mem_npc)).toUInt // mispredicted branch
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i
io.imem.flush_tlb := csr.io.fatc
io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt
io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt || take_pc_mem
io.imem.btb_update.valid := mem_reg_valid && !mem_npc_misaligned && mem_wrong_npc && mem_cfi_taken && !take_pc_wb
io.imem.btb_update.bits.isJump := mem_ctrl.jal || mem_ctrl.jalr