Remove unnecessary muxes in RV32 MulDiv
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parent
9aa724706e
commit
5442b89664
@ -58,13 +58,16 @@ class MulDiv(
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FN_MULHU -> List(Y, Y, N, N),
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FN_MULHSU -> List(Y, Y, Y, N))).map(_ toBool)
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def sext(x: Bits, signed: Bool) = {
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val sign = signed && Mux(io.req.bits.dw === DW_64, x(w-1), x(w/2-1))
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val hi = Mux(io.req.bits.dw === DW_64, x(w-1,w/2), Fill(w/2, sign))
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require(w == 32 || w == 64)
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def halfWidth(req: MultiplierReq) = Bool(w > 32) && req.dw === DW_32
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def sext(x: Bits, halfW: Bool, signed: Bool) = {
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val sign = signed && Mux(halfW, x(w/2-1), x(w-1))
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val hi = Mux(halfW, Fill(w/2, sign), x(w-1,w/2))
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(Cat(hi, x(w/2-1,0)), sign)
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}
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, lhsSigned)
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, rhsSigned)
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val (lhs_in, lhs_sign) = sext(io.req.bits.in1, halfWidth(io.req.bits), lhsSigned)
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val (rhs_in, rhs_sign) = sext(io.req.bits.in2, halfWidth(io.req.bits), rhsSigned)
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val subtractor = remainder(2*w,w) - divisor(w,0)
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val less = subtractor(w)
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@ -143,7 +146,7 @@ class MulDiv(
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}
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io.resp.bits := req
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io.resp.bits.data := Mux(req.dw === DW_32, Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
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io.resp.bits.data := Mux(halfWidth(req), Cat(Fill(w/2, remainder(w/2-1)), remainder(w/2-1,0)), remainder(w-1,0))
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io.resp.valid := state === s_done
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io.req.ready := state === s_ready
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}
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