Support larger I$ sets when VM is disabled
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3b35c7470e
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f14d87e327
@ -103,7 +103,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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io.mem <> icache.io.mem
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icache.io.req.valid := !stall && !s0_same_block
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icache.io.req.bits.idx := io.cpu.npc
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icache.io.req.bits.addr := io.cpu.npc
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icache.io.invalidate := io.cpu.flush_icache
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icache.io.s1_ppn := tlb.io.resp.ppn
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icache.io.s1_kill := io.cpu.req.valid || tlb.io.resp.miss || tlb.io.resp.xcpt_if || icmiss || io.cpu.flush_tlb
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@ -14,8 +14,8 @@ trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
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val refillCycles = refillCyclesPerBeat*outerDataBeats
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}
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class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) {
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val idx = UInt(width = pgIdxBits)
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class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
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val addr = UInt(width = vaddrBits)
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}
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class ICacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasL1CacheParameters {
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@ -35,7 +35,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
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}
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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require(pgIdxBits >= untagBits)
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require(!usingVM || pgIdxBits >= untagBits)
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val s_ready :: s_request :: s_refill_wait :: s_refill :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
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@ -47,27 +47,26 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
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val s1_any_tag_hit = Wire(Bool())
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val s1_valid = Reg(init=Bool(false))
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val s1_pgoff = Reg(UInt(width = pgIdxBits))
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val s1_addr = Cat(io.s1_ppn, s1_pgoff).toUInt
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val s1_tag = s1_addr(tagBits+untagBits-1,untagBits)
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val s1_vaddr = Reg(UInt())
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val s1_paddr = Cat(io.s1_ppn, s1_vaddr(pgIdxBits-1,0)).toUInt
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val s1_tag = s1_paddr(tagBits+untagBits-1,untagBits)
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val s0_valid = io.req.valid || s1_valid && stall
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val s0_pgoff = Mux(s1_valid && stall, s1_pgoff, io.req.bits.idx)
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val s0_vaddr = Mux(s1_valid && stall, s1_vaddr, io.req.bits.addr)
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s1_valid := io.req.valid && rdy || s1_valid && stall && !io.s1_kill
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when (io.req.valid && rdy) {
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s1_pgoff := io.req.bits.idx
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s1_vaddr := io.req.bits.addr
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}
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val out_valid = s1_valid && !io.s1_kill && state === s_ready
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val s1_idx = s1_addr(untagBits-1,blockOffBits)
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val s1_offset = s1_addr(blockOffBits-1,0)
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val s1_idx = s1_vaddr(untagBits-1,blockOffBits)
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val s1_hit = out_valid && s1_any_tag_hit
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val s1_miss = out_valid && !s1_any_tag_hit
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rdy := state === s_ready && !s1_miss
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when (s1_valid && state === s_ready && s1_miss) {
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refill_addr := s1_addr
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refill_addr := s1_paddr
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}
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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@ -79,7 +78,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
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val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
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val entagbits = code.width(tagBits)
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val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = entagbits)))
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val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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when (refill_done) {
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val tag = code.encode(refill_tag).toUInt
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tag_array.write(s1_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
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@ -102,7 +101,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
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val s1_dout = Wire(Vec(nWays, Bits(width = rowBits)))
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for (i <- 0 until nWays) {
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
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val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_vaddr(untagBits-1,blockOffBits))).toBool
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val tag_out = tag_rdata(i)
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val s1_tag_disparity = code.decode(tag_out).error
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s1_tag_match(i) := tag_out(tagBits-1,0) === s1_tag
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@ -119,7 +118,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
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if(refillCycles > 1) data_array.write(Cat(s1_idx, refill_cnt), e_d)
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else data_array.write(s1_idx, e_d)
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}
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val s0_raddr = s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
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val s0_raddr = s0_vaddr(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
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s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid)
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}
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