Add uncached support to blocking D$
This commit is contained in:
Andrew Waterman
parent
42f079ce57
commit
3b35c7470e
@ -126,10 +126,13 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val s2_hit_dirty = s2_hit && s2_hit_state.requiresVoluntaryWriteback()
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val s2_valid_hit = s2_valid_masked && s2_hit
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val s2_valid_miss = s2_valid_masked && !s2_hit && !(pstore1_valid || pstore2_valid)
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val s2_repl = RegEnable(meta.io.resp(replacer.way), s1_valid_not_nacked)
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val s2_repl_dirty = s2_repl.coh.requiresVoluntaryWriteback()
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io.cpu.s2_nack := s2_valid && !s2_valid_hit
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when (io.cpu.s2_nack) { s1_nack := true }
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val s2_uncached = !addrMap.isCacheable(s2_req.addr)
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val s2_valid_cached_miss = s2_valid_miss && !s2_uncached
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val s2_valid_uncached = s2_valid_miss && s2_uncached
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val s2_victim_state = RegEnable(meta.io.resp(replacer.way), s1_valid_not_nacked)
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val s2_victim_dirty = s2_victim_state.coh.requiresVoluntaryWriteback()
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io.cpu.s2_nack := s2_valid && !s2_valid_hit && !(s2_valid_uncached && io.mem.acquire.ready)
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when (s2_valid && !s2_valid_hit) { s1_nack := true }
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// exceptions
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val misaligned = new StoreGen(s1_req.typ, s1_req.addr, UInt(0), wordBytes).misaligned
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@ -174,10 +177,11 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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pstore1_valid := {
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val s2_store_valid = s2_valid_hit && isWrite(s2_req.cmd) && !s2_sc_fail
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val pstore1_held = Reg(Bool())
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assert(!s2_store_valid || !pstore1_held)
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pstore1_held := (s2_store_valid || pstore1_held) && pstore2_valid && !pstore_drain
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s2_store_valid || pstore1_held
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}
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val advance_pstore1 = pstore1_valid && (!pstore2_valid || pstore_drain)
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val advance_pstore1 = pstore1_valid && !(pstore2_valid && !pstore_drain)
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pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1
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val pstore2_addr = RegEnable(pstore1_addr, advance_pstore1)
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val pstore2_way = RegEnable(pstore1_way, advance_pstore1)
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@ -201,24 +205,50 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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when (s1_valid && s1_raw_hazard) { s1_nack := true }
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val s2_new_hit_state = s2_hit_state.onHit(s2_req.cmd)
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metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_hit_state =/= s2_new_hit_state) || (s2_valid_miss && !s2_repl_dirty)
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metaWriteArb.io.in(0).valid := (s2_valid_hit && s2_hit_state =/= s2_new_hit_state) || (s2_valid_cached_miss && !s2_victim_dirty)
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metaWriteArb.io.in(0).bits.way_en := Mux(s2_hit, s2_hit_way, UIntToOH(replacer.way))
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metaWriteArb.io.in(0).bits.idx := s2_req.addr(idxMSB, idxLSB)
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metaWriteArb.io.in(0).bits.data.coh := Mux(s2_hit, s2_new_hit_state, ClientMetadata.onReset)
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metaWriteArb.io.in(0).bits.data.tag := s2_req.addr(paddrBits-1, untagBits)
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// acquire
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io.mem.acquire.valid := s2_valid_miss && !s2_repl_dirty && fq.io.enq.ready
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io.mem.acquire.bits := s2_hit_state.makeAcquire(addr_block = s2_req.addr(paddrBits-1, blockOffBits), client_xact_id = UInt(0), op_code = s2_req.cmd)
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val cachedGetMessage = s2_hit_state.makeAcquire(
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client_xact_id = UInt(0),
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addr_block = s2_req.addr(paddrBits-1, blockOffBits),
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op_code = s2_req.cmd)
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val uncachedGetMessage = Get(
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client_xact_id = UInt(0),
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addr_block = s2_req.addr(paddrBits-1, blockOffBits),
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addr_beat = s2_req.addr(blockOffBits-1, beatOffBits),
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addr_byte = s2_req.addr(beatOffBits-1, 0),
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operand_size = s2_req.typ,
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alloc = Bool(false))
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val uncachedPutMessage = Put(
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client_xact_id = UInt(0),
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addr_block = s2_req.addr(paddrBits-1, blockOffBits),
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addr_beat = s2_req.addr(blockOffBits-1, beatOffBits),
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data = Fill(beatWords, pstore1_storegen.data),
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wmask = pstore1_storegen.mask << (s2_req.addr(beatOffBits-1, wordOffBits) << wordOffBits),
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alloc = Bool(false))
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io.mem.acquire.valid := ((s2_valid_cached_miss && !s2_victim_dirty) || s2_valid_uncached) && fq.io.enq.ready
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io.mem.acquire.bits := cachedGetMessage
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when (s2_uncached) {
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assert(!s2_valid_masked || !s2_hit, "cache hit on uncached access")
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io.mem.acquire.bits := uncachedGetMessage
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when (isWrite(s2_req.cmd)) {
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assert(!s2_valid || !isRead(s2_req.cmd), "uncached AMOs are unsupported")
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io.mem.acquire.bits := uncachedPutMessage
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}
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}
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when (io.mem.acquire.fire()) { grant_wait := true }
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// grant
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val grantIsRefill = io.mem.grant.bits.hasMultibeatData()
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val grantHasData = io.mem.grant.bits.hasData()
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val grantIsUncached = grantHasData && !grantIsRefill
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val grantIsVoluntary = io.mem.grant.bits.isVoluntary()
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val grantIsUncached = !grantIsRefill && !grantIsVoluntary
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when (io.mem.grant.valid) {
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assert(grantIsRefill === io.mem.grant.bits.requiresAck(), "")
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assert(!grantIsUncached, "TODO uncached")
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assert(grant_wait || grantIsVoluntary, "unexpected grant")
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when (grantIsUncached) { s2_data := io.mem.grant.bits.data }
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}
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val (refillCount, refillDone) = Counter(io.mem.grant.fire() && grantIsRefill, refillCycles)
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val grantDone = refillDone || grantIsUncached
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@ -227,7 +257,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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// data refill
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dataArb.io.in(1).valid := grantIsRefill && io.mem.grant.valid
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io.mem.grant.ready := true
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assert(dataArb.io.in(1).ready || !dataArb.io.in(1).valid, "")
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assert(dataArb.io.in(1).ready || !dataArb.io.in(1).valid)
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dataArb.io.in(1).bits.write := true
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dataArb.io.in(1).bits.addr := Cat(s2_req.addr(paddrBits-1, blockOffBits), io.mem.grant.bits.addr_beat) << beatOffBits
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dataArb.io.in(1).bits.way_en := UIntToOH(replacer.way)
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@ -235,12 +265,21 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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dataArb.io.in(1).bits.wmask := ~UInt(0, rowBytes)
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// tag updates on refill
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metaWriteArb.io.in(1).valid := refillDone
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assert(!metaWriteArb.io.in(1).valid || metaWriteArb.io.in(1).ready, "")
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assert(!metaWriteArb.io.in(1).valid || metaWriteArb.io.in(1).ready)
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metaWriteArb.io.in(1).bits.way_en := UIntToOH(replacer.way)
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metaWriteArb.io.in(1).bits.idx := s2_req.addr(idxMSB, idxLSB)
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metaWriteArb.io.in(1).bits.data.coh := s2_hit_state.onGrant(io.mem.grant.bits, s2_req.cmd)
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metaWriteArb.io.in(1).bits.data.tag := s2_req.addr(paddrBits-1, untagBits)
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// finish
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fq.io.enq.valid := io.mem.grant.fire() && io.mem.grant.bits.requiresAck() && (!grantIsRefill || refillDone)
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fq.io.enq.bits := io.mem.grant.bits.makeFinish()
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io.mem.finish <> fq.io.deq
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when (fq.io.enq.valid) {
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assert(fq.io.enq.ready)
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replacer.miss
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}
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// probe
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val block_probe = releaseInFlight || lrscValid || (s2_valid_hit && s2_lr)
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metaReadArb.io.in(0).valid := io.mem.probe.valid && !block_probe
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@ -248,29 +287,24 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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metaReadArb.io.in(0).bits.idx := io.mem.probe.bits.addr_block
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metaReadArb.io.in(0).bits.way_en := ~UInt(0, nWays)
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// finish
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fq.io.enq.valid := refillDone
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fq.io.enq.bits := io.mem.grant.bits.makeFinish()
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io.mem.finish <> fq.io.deq
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when (fq.io.enq.valid) {
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assert(fq.io.enq.ready, "")
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replacer.miss
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}
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// release
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val (writebackCount, writebackDone) = Counter(io.mem.release.fire() && inWriteback, refillCycles)
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val releaseDone = writebackDone || (io.mem.release.fire() && !inWriteback)
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val new_coh = Wire(init = s2_hit_state.onProbe(probe_bits))
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val release_way = Wire(init = s2_hit_way)
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val releaseWay = Wire(init = s2_hit_way)
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val releaseRejected = io.mem.release.valid && !io.mem.release.ready
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val s1_release_data_valid = Reg(next = dataArb.io.in(2).fire())
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val s2_release_data_valid = Reg(next = s1_release_data_valid && !releaseRejected)
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val releaseDataBeat = Cat(UInt(0), writebackCount) + Mux(releaseRejected, UInt(0), s1_release_data_valid + Cat(UInt(0), s2_release_data_valid))
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io.mem.release.valid := s2_release_data_valid
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io.mem.release.bits := ClientMetadata.onReset.makeRelease(probe_bits)
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when (s2_valid_miss && s2_repl_dirty) {
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val voluntaryReleaseMessage = s2_hit_state.makeVoluntaryWriteback(UInt(0), UInt(0))
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val voluntaryNewCoh = s2_hit_state.onCacheControl(M_FLUSH)
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val probeResponseMessage = s2_hit_state.makeRelease(probe_bits)
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val probeNewCoh = s2_hit_state.onProbe(probe_bits)
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val newCoh = Wire(init = probeNewCoh)
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when (s2_valid_cached_miss && s2_victim_dirty) {
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release_state := s_voluntary_writeback
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probe_bits.addr_block := Cat(s2_repl.tag, s2_req.addr(idxMSB, idxLSB))
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probe_bits.addr_block := Cat(s2_victim_state.tag, s2_req.addr(idxMSB, idxLSB))
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}
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when (s2_probe) {
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when (s2_hit_dirty) { release_state := s_probe_rep_dirty }
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@ -285,13 +319,13 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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io.mem.release.valid := true
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}
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when (release_state === s_probe_rep_clean || release_state === s_probe_rep_dirty) {
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io.mem.release.bits := s2_hit_state.makeRelease(probe_bits)
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io.mem.release.bits := probeResponseMessage
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when (releaseDone) { release_state := s_probe_write_meta }
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}
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when (release_state === s_voluntary_writeback || release_state === s_voluntary_write_meta) {
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io.mem.release.bits := s2_hit_state.makeVoluntaryWriteback(UInt(0), UInt(0))
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new_coh := s2_hit_state.onCacheControl(M_FLUSH)
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release_way := UIntToOH(replacer.way)
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io.mem.release.bits := voluntaryReleaseMessage
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newCoh := voluntaryNewCoh
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releaseWay := UIntToOH(replacer.way)
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when (releaseDone) { release_state := s_voluntary_write_meta }
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}
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when (s2_probe && !io.mem.release.fire()) { s1_nack := true }
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@ -305,20 +339,28 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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dataArb.io.in(2).bits.way_en := ~UInt(0, nWays)
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metaWriteArb.io.in(2).valid := (release_state === s_voluntary_write_meta || release_state === s_probe_write_meta)
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metaWriteArb.io.in(2).bits.way_en := release_way
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metaWriteArb.io.in(2).bits.way_en := releaseWay
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metaWriteArb.io.in(2).bits.idx := io.mem.release.bits.full_addr()(idxMSB, idxLSB)
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metaWriteArb.io.in(2).bits.data.coh := new_coh
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metaWriteArb.io.in(2).bits.data.coh := newCoh
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metaWriteArb.io.in(2).bits.data.tag := io.mem.release.bits.full_addr()(paddrBits-1, untagBits)
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when (metaWriteArb.io.in(2).fire()) { release_state := s_ready }
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// response
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io.cpu.replay_next := io.mem.grant.valid && grantIsUncached
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io.cpu.resp.valid := s2_valid_hit || io.cpu.resp.bits.replay
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io.cpu.resp.bits := s2_req // TODO uncached
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io.cpu.resp.bits.has_data := isRead(s2_req.cmd) // TODO uncached
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io.cpu.resp.bits.replay := Reg(next = io.cpu.replay_next)
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// cached response
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io.cpu.resp.valid := s2_valid_hit
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io.cpu.resp.bits := s2_req
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io.cpu.resp.bits.has_data := isRead(s2_req.cmd)
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io.cpu.resp.bits.replay := false
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io.cpu.ordered := !(s1_valid || s2_valid || grant_wait)
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// uncached response
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io.cpu.replay_next := io.mem.grant.valid && grantIsUncached
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val doUncachedResp = Reg(next = io.cpu.replay_next)
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when (doUncachedResp) {
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assert(!s2_valid_hit)
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io.cpu.resp.valid := true
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io.cpu.resp.bits.replay := true
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}
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// load data subword mux/sign extension
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val s2_word_idx = s2_req.addr(log2Up(rowWords*coreDataBytes)-1, log2Up(wordBytes))
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val s2_data_word = s2_data >> Cat(s2_word_idx, UInt(0, log2Up(coreDataBits)))
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@ -338,6 +380,5 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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pstore1_storegen_data := amoalu.io.out
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} else {
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assert(!(s1_valid_masked && isRead(s1_req.cmd) && isWrite(s1_req.cmd)), "unsupported D$ operation")
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assert(!pstore_drain_structural, "???")
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}
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}
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