riscv/rocket-chip
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ahb: eliminate now-unnecesary non-standard hreadyin

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This commit is contained in:
Wesley W. Terpstra 2016-05-18 16:46:28 -07:00
parent 15cad8414d
commit 1db40687c6
2 changed files with 2 additions and 3 deletions
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3
junctions/src/main/scala/hasti.scala
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@ -91,7 +91,6 @@ class HastiSlaveIO(implicit p: Parameters) extends HastiBundle()(p) {
val hrdata = Bits(OUTPUT, hastiDataBits)
val hsel = Bool(INPUT)
val hreadyin = Bool(INPUT) // !!! non-standard signal
val hready = Bool(OUTPUT)
val hresp = UInt(OUTPUT, SZ_HRESP)
}
@ -323,7 +322,7 @@ class HastiSlaveToMaster(implicit p: Parameters) extends HastiModule()(p) {
val out = new HastiMasterIO
}
io.out.htrans := Mux(io.in.hsel && io.in.hreadyin, io.in.htrans, HTRANS_IDLE)
io.out.htrans := Mux(io.in.hsel, io.in.htrans, HTRANS_IDLE)
io.out.hmastlock := io.in.hmastlock
io.out.haddr := io.in.haddr
io.out.hwrite := io.in.hwrite

2
junctions/src/main/scala/poci.scala
View File

@ -23,7 +23,7 @@ class HastiToPociBridge(implicit p: Parameters) extends HastiModule()(p) {
val s_idle :: s_setup :: s_access :: Nil = Enum(UInt(), 3)
val state = Reg(init = s_idle)
val transfer = io.in.hsel & io.in.hreadyin & io.in.htrans(1)
val transfer = io.in.hsel & io.in.htrans(1)
switch (state) {
is (s_idle) {