riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman dd85f2410f Avoid need for cloneType 2016-06-05 23:47:56 -07:00
Andrew Waterman 631e3e2dd9 Make PRCI a singleton, not per-tile 
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
 2016-06-05 23:06:21 -07:00
Andrew Waterman be7500e4a9 Update PLIC addr map 2016-06-05 23:04:51 -07:00
Andrew Waterman 2e88ffc364 Cope with changes to AddrMap 2016-06-03 13:48:09 -07:00
Andrew Waterman f1745bf142 Allow PLIC nPriorities=0 (priority fixed at 1) 2016-06-02 13:48:29 -07:00
Andrew Waterman b7ca2145b3 Fix PLIC control bug when !grant.ready 2016-06-02 13:47:59 -07:00
Andrew Waterman 0866b4c045 Can't assign to Vec literals 2016-06-01 23:36:34 -07:00
Andrew Waterman 20e1de08da Avoid chisel2 pitfall 
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
 2016-06-01 23:35:49 -07:00
Andrew Waterman 5629fb62bf Avoid bitwise sub-assignment 2016-06-01 21:59:02 -07:00
Andrew Waterman 9518b3d589 Fix arithmetic in ROM row count 2016-06-01 21:59:02 -07:00
Andrew Waterman 8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
Andrew Waterman 6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Andrew Waterman 8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
Andrew Waterman 391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect 
We should eventually parameterize this, of course.
 2016-05-26 16:10:42 -07:00
Andrew Waterman b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
Andrew Waterman 8139f71dfb Work around Chisel2 bug 
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
 2016-05-26 12:37:31 -07:00
Andrew Waterman 22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
Andrew Waterman e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman 3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Andrew Waterman 88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
Andrew Waterman 533b229175 Improve PLIC QoR 2016-05-10 17:03:56 -07:00
Andrew Waterman e15e9c5085 First draft of interrupt controller 2016-05-10 00:25:13 -07:00
Andrew Waterman cc4102f8de Add trivial version of PRCI block 
It doesn't really do anything besides deliver deliver IPIs yet.
 2016-05-02 17:49:10 -07:00
Andrew Waterman 72731de25a Take a stab at the PRCI-Rocket interface 2016-05-02 15:20:33 -07:00
Andrew Waterman 695c4c5096 Support both Get and GetBlock on ROMSlave 2016-04-30 17:34:12 -07:00
Andrew Waterman 1df68a25fd Address Map refactoring 2016-04-28 16:08:58 -07:00
Andrew Waterman 81ff127dc3 Clean up TileLinkRecursiveInterconnect a bit 2016-04-27 14:53:11 -07:00
Andrew Waterman 87cecc336f Add new RTC as TileLink slave, not AXI master 2016-04-27 11:55:35 -07:00
Andrew Waterman eb0b5ec61e Remove stats CSR 2016-04-27 00:16:21 -07:00
Andrew Waterman 9044a4a4b7 Replace NastiROM with ROMSlave, which uses TileLink 
I'm not wedded to the name.
 2016-04-27 00:15:30 -07:00
Andrew Waterman 356efe2fd5 Simplify TileLink Narrower 
It's not necessary to use addr_beat to determine where to put the Grant
data.  Just stripe it across all lanes.

This also gets rid of a dependence on addr_beat in Grant.  If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
 2016-04-26 16:44:54 -07:00
Andrew Waterman 8957b5e973 Improve simulation speed of BasicCrossbar 2016-04-01 13:28:11 -07:00
Andrew Waterman 2eafc4c8f3 Extend AMOALU to support RV32 2016-03-10 17:32:23 -08:00
Andrew Waterman c28d115b30 Chisel3 compatibility fix 2016-03-10 17:32:23 -08:00
Andrew Waterman 36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction 2016-03-03 16:57:16 -08:00
Andrew Waterman 2946bc928e Avoid muxing between bundles of different size 2016-01-16 19:01:24 -08:00
Andrew Waterman 0b90b8fe5f Avoid zero-width wire case :-/ 2016-01-12 15:32:29 -08:00
Andrew Waterman a953ff384a Chisel3 compatibility: use more concrete types 2016-01-12 15:32:14 -08:00
Andrew Waterman e52685f2e9 Fix LoadGen zero flag 2015-11-25 20:52:30 -08:00
Andrew Waterman 27df04354f Add ROM with NASTI interface 2015-11-25 20:04:31 -08:00
Andrew Waterman 57e82442a1 Make LoadGen and StoreGen generic 2015-11-24 18:12:42 -08:00
Andrew Waterman d426ecee78 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:52:24 -08:00
Andrew Waterman 0fe16ac1c0 Chisel3 compatibility fixes 2015-09-30 14:37:00 -07:00
Andrew Waterman 3b1da4c57e Revert "replace remaining uses of Vec.fill" 
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
 2015-09-25 17:06:57 -07:00
Andrew Waterman 20b7a82ab6 Use Vec.fill, not Vec.apply, when making Vec literals 2015-09-25 17:06:52 -07:00
Andrew Waterman 2179cb64ae Let isRead be true for store-conditional 
This works around a deadlock bug in the L1 D$, and is arguably true.
 2015-09-25 15:28:02 -07:00
Andrew Waterman 24389a5257 Chisel3 compatibility fixes 2015-09-11 15:41:39 -07:00
Andrew Waterman 350d530766 Use Vec.fill, not Vec.apply, for Vec literals 2015-08-27 10:00:43 -07:00
Andrew Waterman 94287fed90 Avoid type-unsafe assignments 2015-08-27 09:57:36 -07:00
Andrew Waterman 05d311c517 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:47:02 -07:00
Andrew Waterman 01fc61ba96 Don't construct so many Vecs 2015-08-05 18:43:59 -07:00
Andrew Waterman eb6583d607 use cloneType in PhysicalNetworkIO 2015-08-05 16:47:49 -07:00
Andrew Waterman 798ddeb5f5 Chisel3 compatibility: use >>Int instead of >>UInt 
The latter doesn't contract widths anymore.
 2015-08-04 13:15:17 -07:00
Andrew Waterman fb718f03c1 bump scala to 2.11.6 2015-08-03 19:50:58 -07:00
Andrew Waterman 77cf26aeba Chisel3: Flip order of := and <> 2015-08-03 18:53:39 -07:00
Andrew Waterman 121e4fb511 Flip direction of some bulk connects 2015-08-03 18:01:14 -07:00
Andrew Waterman a21979a2fa Bits -> UInt 2015-08-03 18:01:06 -07:00
Andrew Waterman 9c7a41e8d3 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:09:00 -07:00
Andrew Waterman 6fc807f069 Chisel3: Avoid subword assignment 2015-08-01 21:08:35 -07:00
Andrew Waterman 6d574f8c1b Fix incompatible assignment 2015-07-31 00:59:34 -07:00
Andrew Waterman 377e17e811 Add Wire() wrap 2015-07-31 00:32:02 -07:00
Andrew Waterman 0686bdbe28 Avoid cross-module references 
You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
 2015-07-30 23:49:06 -07:00
Andrew Waterman 8f7b390353 UInt-> Bits; avoid mixed UInt/SInt code 2015-07-30 23:49:06 -07:00
Andrew Waterman 6c391e3b37 Use UInt(0), not UInt(width=0), for constant 0 2015-07-30 23:49:06 -07:00
Andrew Waterman a69c749249 Fix compilation with scala 2.11.6 
We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
 2015-07-28 16:24:45 -07:00
Andrew Waterman f8ec6d6393 Chisel3 compatibility: use BitPat for don't-cares 
Also, call the UInt factory instead of the Bits one, for good measure.
 2015-07-28 02:46:23 -07:00
Andrew Waterman 0e06c941df Chisel3 compatibility fixes 2015-07-23 14:58:46 -07:00
Andrew Waterman 3c0475e08b Add Wire() wrap 2015-07-15 20:24:03 -07:00
Andrew Waterman 2d6b3b2331 Don't use clone 2015-07-15 18:06:27 -07:00
Andrew Waterman 276f53b652 Delete BigMem; it's not used anymore 2015-07-15 17:41:47 -07:00
Andrew Waterman 15cec0eab7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:44:54 -07:00
Andrew Waterman e76a9d3493 Chisel3: Don't mix Mux types 2015-07-11 14:05:39 -07:00
Andrew Waterman 5dc3da008e Use Chisel3 SeqMem construct 2015-07-11 13:36:26 -07:00
Andrew Waterman 55059632c4 Temporarily use HTIF to push RTC value to cores 2015-07-05 16:19:39 -07:00
Andrew Waterman b4e38192a1 Fix (?) L2$ miss bug 
The victim's metadata was incorrectly used for the new line.
 2015-06-24 18:01:56 -07:00
Andrew Waterman ea76800d1a Fix data array reset bug 
io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.

This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon.  It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
 2015-06-11 15:28:23 -07:00
Andrew Waterman c941f0a68e New virtual memory implementation (Sv39) 2015-03-27 16:21:29 -07:00
Andrew Waterman 6e540825b2 Use entire 12-bit CSR address 2015-03-14 02:15:24 -07:00
Andrew Waterman d04da83f96 Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00
Andrew Waterman 9bf10ae5d2 remove extraneous toBits (need new Chisel) 2013-09-19 15:26:36 -07:00
Andrew Waterman cc7783404d Add memory command M_XA_XOR 2013-09-12 16:09:53 -07:00
Andrew Waterman 0672773c1a for now, don't use asserts outside of components 2013-05-09 02:14:44 -07:00
Andrew Waterman 7ff5b5b86f treat load-reserved as a non-dirtying store 2013-04-07 19:25:26 -07:00
Andrew Waterman 3479f1c6cd add LR/SC support 2013-04-07 19:25:20 -07:00
Andrew Waterman 944f56a766 remove duplicate definitions 2013-02-28 14:55:19 -08:00
Andrew Waterman 1945fa898b make external clock divider programmable 2013-01-24 23:40:47 -08:00
Andrew Waterman 62a3ea4113 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman 0aa33bf909 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman 1ebfeeca8a add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Andrew Waterman 66cf690261 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00