Chisel3 compatibility fix
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@ -75,7 +75,7 @@ class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) ex
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val rbits = Reg{io.in.bits}
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val active = Reg(init=Bool(false))
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val shifter = Vec(n, Bits(width = narrowWidth))
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val shifter = Wire(Vec(n, Bits(width = narrowWidth)))
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(0 until n).foreach {
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i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth)
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}
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