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riscv
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rocket-chip
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87cecc336fd307789a2d1e749045ed1e368c39ea
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Andrew Waterman
87cecc336f
Add new RTC as TileLink slave, not AXI master
2016-04-27 11:55:35 -07:00
uncore
Add new RTC as TileLink slave, not AXI master
2016-04-27 11:55:35 -07:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%