riscv/rocket-chip
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Andrew Waterman 1ebfeeca8a add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
uncore
add L2$
2012-07-10 05:23:29 -07:00
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Description
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
13 MiB
Languages
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%