riscv/rocket-chip
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15cec0eab7ae1c6052c89933eb8f6e19316a0eeb
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Andrew Waterman 15cec0eab7 Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
uncore
Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
Description
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
13 MiB
Languages
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%