riscv/rocket-chip
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Remove stats CSR

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This commit is contained in:
Andrew Waterman
2016-04-27 00:16:21 -07:00
parent 9044a4a4b7
commit eb0b5ec61e
1 changed files with 0 additions and 7 deletions
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7
uncore/src/main/scala/htif.scala
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@@ -37,7 +37,6 @@ class HostIO(w: Int) extends Bundle {
val clk_edge = Bool(OUTPUT)
val in = Decoupled(Bits(width = w)).flip
val out = Decoupled(Bits(width = w))
val debug_stats_csr = Bool(OUTPUT)
override def cloneType = new HostIO(w).asInstanceOf[this.type]
}
@@ -46,9 +45,6 @@ class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
val reset = Bool(INPUT)
val id = UInt(INPUT, log2Up(nCores))
val csr = new SmiIO(csrDataBits, 12).flip
val debug_stats_csr = Bool(OUTPUT)
// wired directly to stats register
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
}
class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
@@ -59,9 +55,6 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
val scr = new SmiIO(scrDataBits, scrAddrBits)
}
io.host.debug_stats_csr := io.cpu.map(_.debug_stats_csr).reduce(_||_)
// system is 'interesting' if any tile is 'interesting'
val short_request_bits = 64
val long_request_bits = short_request_bits + dataBits*dataBeats
require(short_request_bits % w == 0)