Remove stats CSR
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parent
9044a4a4b7
commit
eb0b5ec61e
@ -37,7 +37,6 @@ class HostIO(w: Int) extends Bundle {
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val clk_edge = Bool(OUTPUT)
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val in = Decoupled(Bits(width = w)).flip
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val out = Decoupled(Bits(width = w))
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val debug_stats_csr = Bool(OUTPUT)
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override def cloneType = new HostIO(w).asInstanceOf[this.type]
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}
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@ -46,9 +45,6 @@ class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(nCores))
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val csr = new SmiIO(csrDataBits, 12).flip
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val debug_stats_csr = Bool(OUTPUT)
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// wired directly to stats register
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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}
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class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHtifParameters {
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@ -59,9 +55,6 @@ class Htif(csr_RESET: Int)(implicit val p: Parameters) extends Module with HasHt
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val scr = new SmiIO(scrDataBits, scrAddrBits)
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}
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io.host.debug_stats_csr := io.cpu.map(_.debug_stats_csr).reduce(_||_)
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// system is 'interesting' if any tile is 'interesting'
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val short_request_bits = 64
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val long_request_bits = short_request_bits + dataBits*dataBeats
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require(short_request_bits % w == 0)
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