Add new RTC as TileLink slave, not AXI master
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@ -44,6 +44,7 @@ class HostIO(w: Int) extends Bundle {
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class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
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val reset = Bool(INPUT)
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val id = UInt(INPUT, log2Up(nCores))
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val timerIRQ = Bool(INPUT)
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val csr = new SmiIO(csrDataBits, 12).flip
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}
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@ -6,59 +6,45 @@ import cde.{Parameters, Field}
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case object RTCPeriod extends Field[Int]
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class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
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class RTC(nHarts: Int)(implicit val p: Parameters) extends Module
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with HasTileLinkParameters
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with HasAddrMapParameters {
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val io = new ClientUncachedTileLinkIO
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val addrTable = Vec.tabulate(nCores) { i =>
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UInt(addrMap(s"conf:csr$i").start + csr_MTIME * csrDataBytes, p(PAddrBits))
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val irqs = Vec(nHarts, Bool()).asOutput
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}
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val rtc = Reg(init=UInt(0, csrDataBits))
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val rtc_tick = Counter(p(RTCPeriod)).inc()
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val w = 64
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val regs = Reg(Vec(nHarts+1, UInt(width = w)))
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require(w == tlDataBits) // TODO relax this constraint for narrower TL
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val sending = Reg(init = Bool(false))
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val send_acked = Reg(init = Vec.fill(nCores)(Bool(true)))
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val coreId = Wire(UInt(width = log2Up(nCores)))
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val acq = Queue(io.tl.acquire, 1)
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when (rtc_tick) {
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rtc := rtc + UInt(1)
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send_acked := Vec.fill(nCores)(Bool(false))
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sending := Bool(true)
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}
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val full_addr = acq.bits.full_addr()
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val byte_addr = full_addr(log2Up(w/8)-1,0)
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val size = w/8*(nHarts+1)
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val addr = full_addr(log2Up(size)-1,log2Up(w/8))
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val rdata = regs(addr)
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val wdata = acq.bits.data
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val read = acq.bits.a_type === Acquire.getType
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val write = acq.bits.a_type === Acquire.putType
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val wmask = acq.bits.full_wmask()
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assert(!acq.valid || read || write, "unsupported RTC operation")
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if (nCores > 1) {
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val (send_cnt, send_done) = Counter(io.acquire.fire(), nCores)
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io.tl.grant.valid := acq.valid
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acq.ready := io.tl.grant.ready
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.bits.getBuiltInGrantType(),
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client_xact_id = acq.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = UInt(0),
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data = rdata)
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when (send_done) { sending := Bool(false) }
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for ((irq, cmp) <- io.irqs zip regs.tail)
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irq := (regs(0) >= cmp)
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coreId := send_cnt
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} else {
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when (io.acquire.fire()) { sending := Bool(false) }
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coreId := UInt(0)
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}
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when (io.grant.fire()) { send_acked(io.grant.bits.client_xact_id) := Bool(true) }
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val addr_full = addrTable(coreId)
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val addr_block = addr_full(p(PAddrBits) - 1, p(CacheBlockOffsetBits))
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val addr_beat = addr_full(p(CacheBlockOffsetBits) - 1, tlByteAddrBits)
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val addr_byte = addr_full(tlByteAddrBits - 1, 0)
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val wmask = Fill(csrDataBytes, UInt(1, 1)) << addr_byte
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io.acquire.valid := sending
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io.acquire.bits := Put(
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client_xact_id = coreId,
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addr_block = addr_block,
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addr_beat = addr_beat,
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wmask = wmask,
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data = Fill(tlDataBytes / csrDataBytes, rtc))
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io.grant.ready := Bool(true)
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require(tlClientXactIdBits >= log2Up(nCores))
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assert(!rtc_tick || send_acked.reduce(_ && _),
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"Not all clocks were updated for rtc tick")
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when (Counter(p(RTCPeriod)).inc()) { regs(0) := regs(0) + UInt(1) }
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when (acq.valid && write) { regs(addr) := wdata & wmask | rdata & ~wmask }
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when (reset) { regs(0) := UInt(0) }
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}
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