Take a stab at the PRCI-Rocket interface
This commit is contained in:
parent
695c4c5096
commit
72731de25a
@ -44,7 +44,6 @@ class HostIO(w: Int) extends Bundle {
|
||||
class HtifIO(implicit p: Parameters) extends HtifBundle()(p) {
|
||||
val reset = Bool(INPUT)
|
||||
val id = UInt(INPUT, log2Up(nCores))
|
||||
val timerIRQ = Bool(INPUT)
|
||||
val csr = new SmiIO(csrDataBits, 12).flip
|
||||
}
|
||||
|
||||
|
25
uncore/src/main/scala/prci.scala
Normal file
25
uncore/src/main/scala/prci.scala
Normal file
@ -0,0 +1,25 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package uncore
|
||||
|
||||
import Chisel._
|
||||
import Chisel.ImplicitConversions._
|
||||
import junctions._
|
||||
import junctions.NastiConstants._
|
||||
import cde.{Parameters, Field}
|
||||
|
||||
/** Number of tiles */
|
||||
case object NTiles extends Field[Int]
|
||||
|
||||
class PRCICoreIO(implicit p: Parameters) extends Bundle {
|
||||
val reset = Bool(OUTPUT)
|
||||
val id = UInt(OUTPUT, log2Up(p(NTiles)))
|
||||
val interrupts = new Bundle {
|
||||
val mtip = Bool()
|
||||
val msip = Bool()
|
||||
val meip = Bool()
|
||||
val seip = Bool()
|
||||
}.asOutput
|
||||
|
||||
override def cloneType: this.type = new PRCICoreIO().asInstanceOf[this.type]
|
||||
}
|
Loading…
Reference in New Issue
Block a user