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rocket-chip
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391a9b91100869b41e706c7a662c6a062e4528ce
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Andrew Waterman
391a9b9110
Use buses, rather than crossbars, by default in TLInterconnect
...
We should eventually parameterize this, of course.
2016-05-26 16:10:42 -07:00
uncore
Use buses, rather than crossbars, by default in TLInterconnect
2016-05-26 16:10:42 -07:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%