riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
280 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
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Andrew Waterman d04da83f96 Make data RAMs 1RW instead of 1R1W
2014-12-15 17:36:17 -08:00
uncore Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00