riscv/rocket-chip
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Author SHA1 Message Date
Andrew WatermanandGitHub 9326cfd64a Merge branch 'master' into incisive-fixes 2016-10-23 23:08:01 -07:00
Andrew WatermanandGitHub 2bdf8c2be7 Merge branch 'master' into move-to-util 2016-09-29 14:42:11 -07:00
Andrew WatermanandGitHub f0debb89e4 Merge pull request #314 from ucb-bar/widecounter-reset 
Allow WideCounter to not be reset
 2016-09-18 22:37:40 -07:00
Andrew WatermanandGitHub e66abb5e92 Merge pull request #276 from ucb-bar/nmemchannels-fix 
Pass nMemChannels to coreplex through CoreplexConfig
 2016-09-12 14:05:50 -07:00
Andrew WatermanandGitHub 49bba961cf Merge pull request #259 from ucb-bar/refactor-periphery 
Refactor Periphery
 2016-09-12 12:18:00 -07:00
Andrew WatermanandGitHub e6889ea711 Merge pull request #269 from ucb-bar/tweaks 
Two tweaks to Rocket perf & QoR
 2016-09-09 15:25:15 -07:00
Andrew WatermanandGitHub b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
Andrew WatermanandGitHub 7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
Andrew WatermanandGitHub 58c87bdf32 Merge pull request #245 from ucb-bar/tilelink2.2 
Tilelink2
 2016-09-07 12:56:22 -07:00
Andrew WatermanandGitHub 23d0b31615 Merge branch 'master' into tilelink2.2 2016-09-07 11:47:50 -07:00
Andrew WatermanandGitHub 6872000f5e Merge pull request #239 from ucb-bar/move_rtc 
Move RTC
 2016-09-02 15:17:49 -07:00
Andrew WatermanandGitHub b7181ba49b Merge branch 'master' into test-harness-fixes 2016-08-19 22:53:12 -07:00
Andrew WatermanandGitHub 9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew WatermanandGitHub 70b677ecda Vec considered harmful; use isOneOf instead (#64) 
Vec is heavyweight and really should only be used for I/O and
dynamic indexing.  A recurring pattern in uncore is

    Vec(const1, const2, const3) contains x

which is nice but has a deleterious effect on simulation copilation
and execution time.  This patch proposes an alternative:

    x isOneOf (const1, const2, const3)
    x isOneOf seqOfThings

I think it's also more idiomatic.

This is just a prototype; I'm not wed to the name or implementation.
 2016-07-07 19:25:57 -07:00
Andrew Waterman d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman 5bc78aba99 Merge pull request #15 from terpstra/ahb 
Ahb
 2016-05-24 17:06:03 -07:00
Andrew Waterman c49cb10c74 Merge pull request #42 from terpstra/ahb 
Ahb
 2016-05-24 17:02:15 -07:00
Andrew Waterman 5ce3527b88 Merge pull request #32 from ucb-bar/pr-btb-masking 
separate btb response mask from the frontend mask
 2016-03-26 18:15:14 -07:00
Andrew Waterman d1639416cb Merge pull request #77 from ucb-bar/chisel3 
Preliminary Chisel 3 Support
 2016-03-24 12:56:36 -07:00
Andrew Waterman 137b77d780 Merge pull request #4 from ucb-bar/chisel3 
Work around Chisel3's lack of 0-width wires
 2016-03-15 17:30:34 -07:00
Andrew Waterman 648437e7cb Merge pull request #70 from ucb-bar/add-rv32-support 
Add RV32 test/configuration options
 2016-03-14 17:06:39 -07:00
Andrew Waterman f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman 67ad36d74a Merge pull request #69 from ucb-bar/fix-tabs 
tabs are evil
 2016-03-10 16:17:46 -08:00
Andrew Waterman 3e721fe80b Merge pull request #2 from ucb-bar/chisel3 
Pass a BitPat to Lookup
 2016-03-06 04:27:52 -08:00
Andrew Waterman 640204b221 Merge pull request #66 from ucb-bar/rocc-ptw-refactoring 
RoCC PTW refactoring
 2016-02-25 18:01:01 -08:00
Andrew Waterman 091782ad27 Merge pull request #29 from ucb-bar/rocc-ptw-refactoring 
RoCC PTW refactoring
 2016-02-25 17:57:22 -08:00
Andrew Waterman b4856da819 Merge pull request #6 from ucb-bar/chisel3 
Chisel 3 Support
 2016-02-05 17:15:49 -08:00
Andrew Waterman 70945953a8 Merge pull request #42 from ucb-bar/chisel3 
Chisel 3 support
 2016-02-05 16:01:35 -08:00
Andrew Waterman 7e9d8c7256 Merge pull request #40 from ucb-bar/make-3.82 
Support make-3.82 and newer
 2016-01-28 14:28:27 -08:00
Andrew Waterman 91be080526 Merge pull request #32 from ucb-bar/javamaxpermsize 
Double Java MaxPermSize.
 2015-12-07 13:58:41 -08:00
Andrew Waterman 59ca373146 Merge pull request #18 from jackkoenig/master 
Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
 2015-11-08 22:38:01 -08:00
Andrew Waterman d08b75c472 Merge pull request #15 from ucb-bar/fix_disasm_garbage 
If you don't have spike-disasm in your path, your path is dumped
 2015-09-03 17:55:31 -07:00
Andrew Waterman 25e1412a33 Merge pull request #11 from ucb-bar/regression-fixes 
Regression script fixes
 2015-07-20 12:58:54 -07:00
Andrew Waterman 24bb032ede Merge pull request #7 from ccelio/master 
Rocket front-end can now fetch 4 instructions; added assert to dcache; refactoring
 2015-04-12 19:18:23 -07:00
Andrew Waterman 655f9ae1af Merge pull request #2 from ccelio/master 
Global history now updated (speculatively) in fetch.
 2014-09-30 17:12:15 -07:00
Andrew Waterman 7bffc6c586 rename Unsigned.size to Unsigned.clog2 2014-06-14 13:58:07 -07:00
Andrew Waterman 3828c628c3 Remove vestigial control signals 2014-06-14 13:58:07 -07:00
Andrew Waterman 04593d433e clean up Int <-> Boolean conversion stuff 2014-06-14 13:58:07 -07:00
Andrew Waterman ac88ded35a Use ROMs to reduce node count and improve QoR a bit 2014-06-14 13:58:07 -07:00
Andrew Waterman 88899eafe0 Reduce node count a bit 2014-06-14 13:58:07 -07:00
Andrew Waterman 1ae7a9376c Fix unhandled LLC writeback hazard 2014-06-13 03:25:52 -07:00
Andrew Waterman 8bc1c33540 Fix BTB error (requires Chisel update) 2014-05-19 18:56:30 -07:00
Andrew Waterman 364a6de214 Use Mem instead of Vec[Reg] 2014-05-18 19:26:35 -07:00
Andrew Waterman cbb37ccc3e Use Mem instead of Vec[Reg] 2014-05-18 19:25:43 -07:00
Andrew Waterman e91e12ed88 Fix RoCC accumulator example 2014-05-14 16:17:39 -07:00
Andrew Waterman 4ca152b012 Use BundleWithConf to avoid clone method boilerplate 2014-05-09 19:37:16 -07:00
Andrew Waterman 94c1f01ec6 Deanonymize CSRFile's IO bundle 2014-05-09 19:30:57 -07:00
Andrew Waterman fd5f419eb1 use getWidth instead of width 2014-05-09 19:30:57 -07:00
Andrew Waterman 0c13c00d08 Reduce node count by avoiding elsewhen :-( 2014-05-09 19:30:57 -07:00
Andrew Waterman 8dcc0cbb53 Fix bug with multiple DecodeLogics per module 2014-05-09 19:30:57 -07:00
Andrew Waterman 09e2ec1f9e Fix sign of remainder when dividing by zero 
h/t chris
 2014-04-18 16:32:57 -07:00
Andrew Waterman 3520620fbd Remove D$ -> BTB path 2014-04-15 23:05:02 -07:00
Andrew Waterman de492b3cf7 Fix critical path through integer scoreboard 2014-04-15 21:28:13 -07:00
Andrew Waterman fb8c7d3da5 Push rocket 2014-04-07 23:49:06 -07:00
Andrew Waterman 3ed8adf032 Add early out for MUL[W] (not MULH[[S]U]) 2014-04-07 23:48:02 -07:00
Andrew Waterman 927287da34 Bypass RAS push/pop 2014-04-07 23:47:53 -07:00
Andrew Waterman 817517c663 Better branch prediction 2014-04-07 16:08:06 -07:00
Andrew Waterman f235fa0db6 Move branch resolution to M stage 2014-04-07 15:58:49 -07:00
Andrew Waterman db59fc65ab Add return address stack 2014-04-01 15:01:27 -07:00
Andrew Waterman e3b12e0b85 Make BTB more complexity-effective 
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices.  This makes much larger BTBs feasible.  It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
 2014-03-25 05:22:04 -07:00
Andrew Waterman 804b09c8c5 Frontend QoR tweaks 2014-03-25 05:20:24 -07:00
Andrew Waterman 6465e2df14 Make Int -> Bool conversions explicit 2014-03-24 04:36:53 -07:00
Andrew Waterman 1b030777ce Remove vestigial control signal 2014-03-24 04:36:12 -07:00
Andrew Waterman 51808d9982 Fix minor FP bugs 2014-03-18 18:37:53 -07:00
Andrew Waterman 5996418021 Fix exception behavior of fmin/fmax 2014-03-18 18:36:51 -07:00
Andrew Waterman 0d124d283a Write our own vcs main() routine 2014-03-17 17:02:28 -07:00
Andrew Waterman 7f23257873 Print out random seed if test fails 2014-03-17 15:35:32 -07:00
Andrew Waterman fcbbb275aa Fix nondeterminism 2014-03-15 17:35:30 -07:00
Andrew Waterman 54cbf0c4f1 Add (unused) RV32 CSRs 2014-03-15 17:33:17 -07:00
Andrew Waterman 943d7ac80a Use LinkedHashSet/Map for simpler determinism 2014-03-15 17:31:48 -07:00
Andrew Waterman b6bf7cfe0c push chisel 2014-03-11 23:56:57 -07:00
Andrew Waterman 7ac003a4f7 push hardfloat 2014-03-11 20:36:39 -07:00
Andrew Waterman f04bde75fb New FP encoding 2014-03-11 19:12:20 -07:00
Andrew Waterman a0389645b7 New FP encoding; improved FP implementation 2014-03-11 18:58:24 -07:00
Andrew Waterman 00bc1a2293 Add fclass.{s|d} instructions 2014-03-10 16:59:24 -07:00
Andrew Waterman d055c0ebaf Push rocket/hardfloat/chisel 2014-03-04 16:39:06 -08:00
Andrew Waterman 9f2e16c58a Fix D$ arbiter for >2 inputs 2014-03-04 16:32:17 -08:00
Andrew Waterman fa75f6e81e Fix null pointer exception when HAS_FPU=false 2014-03-04 16:32:09 -08:00
Andrew Waterman c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Andrew Waterman de965d558a Renumber uarch CSRs into custom CSR space 2014-02-14 17:41:17 -08:00
Andrew Waterman e554f6728d Update chisel 2014-02-14 17:41:17 -08:00
Andrew Waterman 8e3ca609f7 Renumber uarch CSRs into custom CSR space 2014-02-14 17:40:00 -08:00
Andrew Waterman 02dbd6b0aa Don't assign to your own inputs 2014-02-12 18:39:40 -08:00
Andrew Waterman e5de170215 Update Chisel, fixing Verilog backend 2014-02-12 14:28:43 -08:00
Andrew Waterman 0ebb115a3c Revert to old AUIPC definition 2014-02-10 19:05:14 -08:00
Andrew Waterman a09ff9fdc7 Revert to old AUIPC definition 2014-02-10 19:04:42 -08:00
Andrew Waterman 1456170c6d Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence 2014-02-06 12:01:49 -08:00
Andrew Waterman 11e69a73cd Fix tests when !hwacha; disable hwacha by default 2014-02-06 03:08:33 -08:00
Andrew Waterman eca8c99f44 Ignore rocc interrupt line when no rocc is present 2014-02-06 03:06:55 -08:00
Andrew Waterman e7a726fbac Make uarch counters read-only 2014-02-06 01:48:56 -08:00
Andrew Waterman 62e9313aef Add 16 microarchitectural counters 2014-02-06 00:13:02 -08:00
Andrew Waterman e9d3a650a4 Speed up C++ compilation 2014-01-31 12:25:19 -08:00
Andrew Waterman febd26f505 Correct CSR privilege logic 2014-01-31 01:03:17 -08:00
Andrew Waterman 0ce98a7e0c Update riscv-tools 2014-01-28 03:52:55 -08:00
Andrew Waterman fb827abbfa Use dynamic fesvr library 2014-01-28 03:50:19 -08:00
Andrew Waterman 0266c1f76a Support retirement width > 1 in CSR file 2014-01-24 16:37:40 -08:00
Andrew Waterman 267394d3cc Fix CSR interlocks 2014-01-24 16:37:40 -08:00
Andrew Waterman 1f986d1c96 Branches don't care about the ALU input/function 2014-01-24 16:37:40 -08:00