Use ROMs to reduce node count and improve QoR a bit
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@ -109,14 +109,12 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
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val decoded_addr = {
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val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size))
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val outs = for (i <- 0 until CSRs.all.size)
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yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size))
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val d = DecodeLogic(addr, default, outs).toArray
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val map = for ((v, i) <- CSRs.all.zipWithIndex)
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yield v -> UInt(BigInt(1) << i)
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val out = ROM(map)(addr)
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val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
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for (i <- 0 until CSRs.all.size)
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a(CSRs.all(i)) = d(0)(i)
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a(CSRs.all(i)) = out(i)
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a
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}
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@ -421,10 +421,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
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legal_csrs --= fp_csrs
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val id_csr_addr = io.dpath.inst(31,20)
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val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i))
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val id_csr_en = id_csr != CSR.N
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val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
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val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
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val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
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val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr)
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val id_csr_privileged = id_csr_en &&
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(id_csr_addr(11,10) === UInt(3) && id_csr_wen ||
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id_csr_addr(11,10) === UInt(2) ||
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