Fix BTB error (requires Chisel update)
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@ -146,14 +146,12 @@ class BTB(implicit conf: BTBConfig) extends Module {
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val nextRepl = Counter(!updateHit && updateValid, conf.entries)._1
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val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
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when (doPageRepl) {
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val clearValid = for (i <- 0 until conf.entries)
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yield (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR
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idxValid := idxValid & ~Vec(clearValid).toBits
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}
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// invalidate entries if we stomp on pages they depend upon
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idxValid := idxValid & ~Vec.tabulate(conf.entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := updateValid
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when (updateTarget) {
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assert(io.req === update.bits.target, "BTB request != I$ target")
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idxValid := idxValid.bitSet(waddr, updateValid)
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idxs(waddr) := update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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