Make BTB more complexity-effective
BTB entries reference a small number of unique pages, so we separate the storage of pages from indices. This makes much larger BTBs feasible. It's easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
This commit is contained in:
Andrew Waterman
parent
804b09c8c5
commit
e3b12e0b85
121
rocket/src/main/scala/btb.scala
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121
rocket/src/main/scala/btb.scala
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@ -0,0 +1,121 @@
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package rocket
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import Chisel._
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import Util._
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import Node._
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import uncore.constants.AddressConstants._
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case class BTBConfig(entries: Int) {
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val matchBits = PGIDX_BITS
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val pages0 = 1 + log2Up(entries) // is this sensible? what about matchBits?
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val pages = (pages0+1)/2*2 // control logic assumes 2 divides pages
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}
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// fully-associative branch target buffer
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class BTB(conf: BTBConfig) extends Module {
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val io = new Bundle {
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val current_pc = UInt(INPUT, VADDR_BITS)
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val hit = Bool(OUTPUT)
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val target = UInt(OUTPUT, VADDR_BITS)
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val wen = Bool(INPUT)
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val taken = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val correct_pc = UInt(INPUT, VADDR_BITS)
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val correct_target = UInt(INPUT, VADDR_BITS)
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}
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val idxValid = Vec.fill(conf.entries){Reg(init=Bool(false))}
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val idxs = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val idxPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val idxPagesOH = idxPages.map(UIntToOH(_)(conf.pages-1,0))
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val tgts = Vec.fill(conf.entries){Reg(UInt(width=conf.matchBits))}
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val tgtPages = Vec.fill(conf.entries){Reg(UInt(width=log2Up(conf.pages)))}
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(conf.pages-1,0))
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val pages = Vec.fill(conf.pages){Reg(UInt(width=VADDR_BITS-conf.matchBits))}
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val pageValid = Vec.fill(conf.pages){Reg(init=Bool(false))}
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private def page(addr: UInt) = addr >> conf.matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid.toBits
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}
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private def tagMatch(addr: UInt): UInt = tagMatch(addr, pageMatch(addr))
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private def tagMatch(addr: UInt, pgMatch: UInt): UInt = {
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val idx = addr(conf.matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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idxValid.toBits & idxMatch & idxPageMatch
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}
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val hits = tagMatch(io.current_pc)
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val idxPageMatch = pageMatch(io.correct_pc)
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val tgtPageMatch = pageMatch(io.correct_target)
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val updates = tagMatch(io.correct_pc, idxPageMatch)
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val anyUpdates = updates.orR
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private var lfsr = LFSR16(io.wen)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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def randOrInvalid(valid: UInt) =
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Mux(!valid.andR, PriorityEncoderOH(~valid), rand(valid.getWidth))
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val idxRepl = randOrInvalid(idxValid.toBits)
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val idxWen = updates.toBits | idxRepl & ~anyUpdates.toSInt
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val useIdxPageMatch = idxPageMatch.orR
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val doIdxPageRepl = !useIdxPageMatch && io.taken
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val idxPageRepl = rand(conf.pages)
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val idxPageUpdate = Mux(useIdxPageMatch, idxPageMatch, idxPageRepl)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(io.correct_pc) === page(io.correct_target)
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val useTgtPageMatch = (tgtPageMatch & ~idxPageReplEn).orR
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val doTgtPageRepl = !useTgtPageMatch && io.taken && !samePage
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val tgtPageRepl = Mux(samePage, idxPageUpdate, idxPageUpdate(conf.pages-2,0) << 1 | idxPageUpdate(conf.pages-1))
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val tgtPageUpdate = Mux(useTgtPageMatch, tgtPageMatch, tgtPageRepl)
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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when (io.wen) {
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for (i <- 0 until conf.entries) {
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when (idxWen(i)) {
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idxValid(i) := io.taken
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when (io.taken) {
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idxs(i) := io.correct_pc
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idxPages(i) := OHToUInt(idxPageUpdate)
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tgts(i) := io.correct_target
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tgtPages(i) := OHToUInt(tgtPageUpdate)
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}
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}.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
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idxValid(i) := false
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}
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}
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require(conf.pages % 2 == 0)
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val idxWritesEven = (idxPageUpdate & Fill(conf.pages/2, UInt(1,2))).orR
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) = {
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for (i <- i until conf.pages by mod) {
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when (en && pageReplEn(i)) {
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pages(i) := data
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pageValid(i) := true
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}
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}
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}
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(io.correct_pc), page(io.correct_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(io.correct_target), page(io.correct_pc)))
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}
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when (io.invalidate) {
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idxValid.foreach(_ := false)
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pageValid.foreach(_ := false)
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}
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io.hit := hits.toBits.orR
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io.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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}
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@ -7,56 +7,6 @@ import uncore.HTIFIO
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import uncore.constants.AddressConstants._
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import scala.math._
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class DpathBTBIO extends Bundle
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{
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val current_pc = UInt(INPUT, VADDR_BITS)
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val hit = Bool(OUTPUT)
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val target = UInt(OUTPUT, VADDR_BITS)
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val wen = Bool(INPUT)
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val clr = Bool(INPUT)
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val invalidate = Bool(INPUT)
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val correct_pc = UInt(INPUT, VADDR_BITS)
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val correct_target = UInt(INPUT, VADDR_BITS)
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}
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// fully-associative branch target buffer
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class rocketDpathBTB(entries: Int) extends Module
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{
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val io = new DpathBTBIO
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var hit_reduction = Bool(false)
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val hit = Bool()
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val update = Bool()
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var update_reduction = Bool(false)
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val valid = Vec.fill(entries){Reg(init=Bool(false))}
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val hits = Vec.fill(entries){Bool()}
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val updates = Vec.fill(entries){Bool()}
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val targets = Vec.fill(entries){Reg(UInt())}
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val anyUpdate = updates.toBits.orR
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val random_way = Random(entries, io.wen)
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val invalid_way = valid.indexWhere((x: Bool) => !x)
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val repl_way = Mux(valid.contains(Bool(false)), invalid_way, random_way)
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for (i <- 0 until entries) {
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val tag = Reg(UInt())
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hits(i) := valid(i) && tag === io.current_pc
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updates(i) := valid(i) && tag === io.correct_pc
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when (io.wen && (updates(i) || !anyUpdate && UInt(i) === repl_way)) {
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valid(i) := Bool(false)
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when (!io.clr) {
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valid(i) := Bool(true)
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tag := io.correct_pc
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targets(i) := io.correct_target
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}
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}
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}
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io.hit := hits.toBits.orR
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io.target := Mux1H(hits, targets)
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}
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class Status extends Bundle {
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val ip = Bits(width = 8)
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val im = Bits(width = 8)
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@ -294,16 +244,3 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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reg_status.ip := 0
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}
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}
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class ioReadPort(d: Int, w: Int) extends Bundle
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{
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override def clone = new ioReadPort(d, w).asInstanceOf[this.type]
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}
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class ioWritePort(d: Int, w: Int) extends Bundle
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{
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val addr = UInt(INPUT, log2Up(d))
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val en = Bool(INPUT)
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val data = Bits(INPUT, w)
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override def clone = new ioWritePort(d, w).asInstanceOf[this.type]
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}
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@ -6,7 +6,7 @@ import Util._
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case class ICacheConfig(sets: Int, assoc: Int,
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ibytes: Int = 4,
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ntlb: Int = 8, nbtb: Int = 8,
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ntlb: Int = 8, btb: BTBConfig = BTBConfig(8),
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code: Code = new IdentityCode)
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{
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val w = 1
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@ -55,7 +55,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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val mem = new UncachedTileLinkIO
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}
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val btb = Module(new rocketDpathBTB(c.nbtb))
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val btb = Module(new BTB(c.btb))
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val icache = Module(new ICache)
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val tlb = Module(new TLB(c.ntlb))
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@ -94,7 +94,7 @@ class Frontend(implicit c: ICacheConfig, tl: TileLinkConfiguration) extends Modu
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btb.io.current_pc := s1_pc
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btb.io.wen := io.cpu.req.bits.mispredict
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btb.io.clr := !io.cpu.req.bits.taken
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btb.io.taken := io.cpu.req.bits.taken
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btb.io.correct_pc := io.cpu.req.bits.currentpc
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btb.io.correct_target := io.cpu.req.bits.pc
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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@ -11,12 +11,15 @@ object Util {
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implicit def intToUInt(x: Int): UInt = UInt(x)
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implicit def booleanToBool(x: Boolean): Bits = Bool(x)
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implicit def intSeqToUIntSeq(x: Iterable[Int]): Iterable[UInt] = x.map(UInt(_))
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implicit def seqToVec[T <: Data](x: Iterable[T]): Vec[T] = Vec(x)
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implicit def wcToUInt(c: WideCounter): UInt = c.value
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implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
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implicit def intToBooleanToInt(x: Int): BooleanToInt = new BooleanToInt(x)
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}
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import Util._
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object AVec
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{
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def apply[T <: Data](elts: Seq[T]): Vec[T] = Vec(elts)
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@ -141,18 +144,20 @@ case class WideCounter(width: Int, inc: UInt = UInt(1))
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object Random
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{
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def apply(mod: Int, inc: Bool = Bool(true)): UInt = {
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if (isPow2(mod)) {
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require(mod <= 65536)
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LFSR16(inc)(log2Up(mod)-1,0).toUInt
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} else {
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val max = 1 << log2Up(mod*8)
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val rand_pow2 = apply(max, inc)
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var res = UInt(mod-1)
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for (i <- mod-1 to 1 by -1)
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res = Mux(rand_pow2 < UInt(i*max/mod), UInt(i-1), res)
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res
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}
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def apply(mod: Int, random: UInt): UInt = {
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if (isPow2(mod)) random(log2Up(mod)-1,0)
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else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
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}
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def apply(mod: Int): UInt = apply(mod, randomizer)
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def oneHot(mod: Int, random: UInt): UInt = {
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if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
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else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).toBits
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}
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def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
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private def randomizer = LFSR16()
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private def round(x: Double): Int =
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if (x.toInt.toDouble == x) x.toInt else (x.toInt + 1) & -2
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private def partition(value: UInt, slices: Int) =
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Vec.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices))
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}
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