Fix critical path through integer scoreboard
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444d0449e3
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@ -601,6 +601,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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wb_reg_rocc_val := mem_reg_rocc_val
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}
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val wb_set_sboard = wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val
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val replay_wb_common =
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io.dmem.resp.bits.nack || wb_reg_replay || io.dpath.csr_replay
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val wb_rocc_val = wb_reg_rocc_val && !replay_wb_common
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@ -625,7 +626,6 @@ class Control(implicit conf: RocketConfiguration) extends Module
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}
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val sboard = new Scoreboard(32)
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sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
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sboard.clear(io.dpath.ll_wen, io.dpath.ll_waddr)
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val id_stall_fpu = if (!conf.fpu.isEmpty) {
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@ -711,18 +711,25 @@ class Control(implicit conf: RocketConfiguration) extends Module
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id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
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// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
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val data_hazard_wb = wb_reg_wen &&
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(id_renx1_not0 && id_raddr1 === io.dpath.wb_waddr ||
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id_renx2_not0 && id_raddr2 === io.dpath.wb_waddr ||
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id_wen_not0 && id_waddr === io.dpath.wb_waddr)
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val fp_data_hazard_wb = wb_reg_fp_wen &&
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(io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr ||
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io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
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io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
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io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
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val id_wb_hazard = fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
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val id_wb_hazard = data_hazard_wb && wb_set_sboard ||
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fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
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val id_sboard_hazard =
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(id_renx1_not0 && sboard.readBypassed(id_raddr1) ||
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id_renx2_not0 && sboard.readBypassed(id_raddr2) ||
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id_wen_not0 && sboard.readBypassed(id_waddr))
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sboard.set(wb_set_sboard && io.dpath.wb_wen, io.dpath.wb_waddr)
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val ctrl_stalld =
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id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
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id_fp_val && id_stall_fpu ||
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