Correct CSR privilege logic
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@ -410,16 +410,18 @@ class Control(implicit conf: RocketConfiguration) extends Module
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val id_csr_en = id_csr != CSR.N
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val id_csr_fp = Bool(conf.fpu) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
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val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
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val id_csr_privileged = id_csr_en &&
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(id_csr_addr(9,8) != UInt(0) ||
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id_csr_addr(11,10) != UInt(0) && id_csr_wen)
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val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
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val id_csr_privileged = id_csr_en &&
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(id_csr_addr(11,10) === UInt(3) && id_csr_wen ||
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id_csr_addr(11,10) === UInt(2) ||
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id_csr_addr(11,10) === UInt(1) && !io.dpath.status.s ||
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id_csr_addr(9,8) >= UInt(2) ||
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id_csr_addr(9,8) === UInt(1) && !io.dpath.status.s && id_csr_wen)
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// flush pipeline on CSR writes that may have side effects
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val id_csr_flush = {
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val safe_csrs = CSRs.sup0 :: CSRs.sup1 :: CSRs.epc :: Nil
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id_csr_en && id_csr_wen && !DecodeLogic(id_csr_addr, safe_csrs, legal_csrs -- safe_csrs)
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}
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val id_privileged = id_sret || id_csr_privileged
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// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
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val id_amo_aq = io.dpath.inst(26)
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@ -436,7 +438,8 @@ class Control(implicit conf: RocketConfiguration) extends Module
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(io.imem.resp.bits.xcpt_ma, UInt(Causes.misaligned_fetch)),
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(io.imem.resp.bits.xcpt_if, UInt(Causes.fault_fetch)),
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(!id_int_val || id_csr_invalid, UInt(Causes.illegal_instruction)),
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(id_privileged && !io.dpath.status.s, UInt(Causes.privileged_instruction)),
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(id_csr_privileged, UInt(Causes.privileged_instruction)),
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(id_sret && !io.dpath.status.s, UInt(Causes.privileged_instruction)),
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((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(Causes.fp_disabled)),
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(id_syscall, UInt(Causes.syscall)),
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(id_rocc_val && !io.dpath.status.er, UInt(Causes.accelerator_disabled))))
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