Merge pull request #2 from ccelio/master
Global history now updated (speculatively) in fetch.
This commit is contained in:
Andrew Waterman
commit
655f9ae1af
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@ -8,7 +8,7 @@ import Node._
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import uncore._
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case object NBTBEntries extends Field[Int]
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case object NRAS extends Field[Int]
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case object NRAS extends Field[Int]
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abstract trait BTBParameters extends UsesParameters {
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val vaddrBits = params(VAddrBits)
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@ -41,21 +41,25 @@ class RAS(nras: Int) {
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}
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class BHTResp extends Bundle with BTBParameters {
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val index = UInt(width = log2Up(nBHT).max(1))
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val history = UInt(width = log2Up(nBHT).max(1))
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val value = UInt(width = 2)
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}
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class BHT(nbht: Int) {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt): BHTResp = {
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val nbhtbits = log2Up(nbht)
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def get(addr: UInt, update: Bool): BHTResp = {
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val res = new BHTResp
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res.index := addr(nbhtbits+1,2) ^ history
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res.value := table(res.index)
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val index = addr(nbhtbits+1,2) ^ history
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res.value := table(index)
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res.history := history
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val taken = res.value(0)
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when (update) { history := Cat(taken, history(nbhtbits-1,1)) }
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res
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}
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def update(d: BHTResp, taken: Bool): Unit = {
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table(d.index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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history := Cat(taken, history(nbhtbits-1,1))
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def update(addr: UInt, d: BHTResp, taken: Bool, mispredict: Bool): Unit = {
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val index = addr(nbhtbits+1,2) ^ d.history
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table(index) := Cat(taken, (d.value(1) & d.value(0)) | ((d.value(1) | d.value(0)) & taken))
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when (mispredict) { history := Cat(taken, d.history(nbhtbits-1,1)) }
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}
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private val table = Mem(UInt(width = 2), nbht)
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@ -81,10 +85,14 @@ class BTBResp extends Bundle with BTBParameters {
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val bht = new BHTResp
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}
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class BTBReq extends Bundle with BTBParameters {
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val addr = UInt(width = vaddrBits)
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}
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// fully-associative branch target buffer
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class BTB extends Module with BTBParameters {
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val io = new Bundle {
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val req = UInt(INPUT, vaddrBits)
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val req = Valid(new BTBReq).flip
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val resp = Valid(new BTBResp)
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val update = Valid(new BTBUpdate).flip
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val invalidate = Bool(INPUT)
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@ -115,23 +123,23 @@ class BTB extends Module with BTBParameters {
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idxValid & idxMatch & idxPageMatch
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}
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val update = Pipe(io.update)
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val update_target = io.req
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val r_update = Pipe(io.update)
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val update_target = io.req.bits.addr
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val pageHit = pageMatch(io.req)
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val hits = tagMatch(io.req, pageHit)
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val updatePageHit = pageMatch(update.bits.pc)
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val updateHits = tagMatch(update.bits.pc, updatePageHit)
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val pageHit = pageMatch(io.req.bits.addr)
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val hits = tagMatch(io.req.bits.addr, pageHit)
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val updatePageHit = pageMatch(r_update.bits.pc)
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val updateHits = tagMatch(r_update.bits.pc, updatePageHit)
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private var lfsr = LFSR16(update.valid)
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private var lfsr = LFSR16(r_update.valid)
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def rand(width: Int) = {
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lfsr = lfsr(lfsr.getWidth-1,1)
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Random.oneHot(width, lfsr)
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}
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val updateHit = update.bits.prediction.valid
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val updateValid = update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && update.bits.incorrectTarget
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val updateHit = r_update.bits.prediction.valid
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val updateValid = r_update.bits.incorrectTarget || updateHit && Bool(nBHT > 0)
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val updateTarget = updateValid && r_update.bits.incorrectTarget
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val useUpdatePageHit = updatePageHit.orR
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val doIdxPageRepl = updateTarget && !useUpdatePageHit
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@ -140,7 +148,7 @@ class BTB extends Module with BTBParameters {
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(update.bits.pc) === page(update_target)
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val samePage = page(r_update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = updateTarget && !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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@ -149,24 +157,24 @@ class BTB extends Module with BTBParameters {
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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idxPageRepl := UIntToOH(Counter(update.valid && doPageRepl, nPages)._1)
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idxPageRepl := UIntToOH(Counter(r_update.valid && doPageRepl, nPages)._1)
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when (update.valid && !(updateValid && !updateTarget)) {
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when (r_update.valid && !(updateValid && !updateTarget)) {
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val nextRepl = Counter(!updateHit && updateValid, entries)._1
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val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
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val waddr = Mux(updateHit, r_update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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idxValid := idxValid & ~Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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idxValid(waddr) := updateValid
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when (updateTarget) {
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assert(io.req === update.bits.target, "BTB request != I$ target")
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idxs(waddr) := update.bits.pc
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assert(io.req.bits.addr === r_update.bits.target, "BTB request != I$ target")
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idxs(waddr) := r_update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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useRAS(waddr) := update.bits.isReturn
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isJump(waddr) := update.bits.isJump
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useRAS(waddr) := r_update.bits.isReturn
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isJump(waddr) := r_update.bits.isJump
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}
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require(nPages % 2 == 0)
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@ -177,9 +185,9 @@ class BTB extends Module with BTBParameters {
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when (en && pageReplEn(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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Mux(idxWritesEven, page(update.bits.pc), page(update_target)))
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Mux(idxWritesEven, page(r_update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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Mux(idxWritesEven, page(update_target), page(update.bits.pc)))
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Mux(idxWritesEven, page(update_target), page(r_update.bits.pc)))
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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}
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@ -196,8 +204,12 @@ class BTB extends Module with BTBParameters {
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val res = bht.get(io.req)
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when (update.valid && updateHit && !update.bits.isJump) { bht.update(update.bits.prediction.bits.bht, update.bits.taken) }
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val res = bht.get(io.req.bits.addr, io.req.valid && hits.orR && !Mux1H(hits, isJump))
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val update_btb_hit = io.update.bits.prediction.valid
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when (io.update.valid && update_btb_hit && !io.update.bits.isJump) {
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bht.update(io.update.bits.pc, io.update.bits.prediction.bits.bht,
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io.update.bits.taken, io.update.bits.incorrectTarget)
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}
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when (!res.value(0) && !Mux1H(hits, isJump)) { io.resp.bits.taken := false }
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io.resp.bits.bht := res
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}
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@ -44,7 +44,7 @@ class Frontend extends FrontendModule
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val cpu = new CPUFrontendIO().flip
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val mem = new UncachedTileLinkIO
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}
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val btb = Module(new BTB)
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val icache = Module(new ICache)
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val tlb = Module(new TLB(params(NITLBEntries)))
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@ -85,7 +85,8 @@ class Frontend extends FrontendModule
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s2_valid := Bool(false)
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}
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btb.io.req := s1_pc & SInt(-coreInstBytes)
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btb.io.req.valid := !stall && !icmiss
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btb.io.req.bits.addr := s1_pc & SInt(-coreInstBytes)
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btb.io.update := io.cpu.btb_update
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btb.io.invalidate := io.cpu.invalidate || io.cpu.ptw.invalidate
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