Remove vestigial control signal
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5996418021
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@ -383,7 +383,6 @@ class Control(implicit conf: RocketConfiguration) extends Module
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val wb_reg_div_mul_val = Reg(init=Bool(false))
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val take_pc = Bool()
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val pc_taken = Reg(next=take_pc, init=Bool(false))
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val take_pc_wb = Bool()
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val ctrl_killd = Bool()
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val ctrl_killx = Bool()
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@ -707,7 +706,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
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ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || ctrl_draind
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io.dpath.killd := take_pc || ctrl_stalld && !ctrl_draind
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io.imem.resp.ready := pc_taken || !ctrl_stalld || ctrl_draind
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io.imem.resp.ready := !ctrl_stalld || ctrl_draind
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io.imem.invalidate := wb_reg_flush_inst
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io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
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