Push rocket/hardfloat/chisel
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2
chisel
2
chisel
Submodule chisel updated: 56e8b23ff2...25a33ba1d4
@ -125,7 +125,7 @@ int main(int argc, char** argv)
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}
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if (log)
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tile.print(stderr, stderr);
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tile.print(stderr);
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if (vcd)
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tile.dump(vcdfile, trace_count);
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Submodule hardfloat updated: d126925915...39a08130d4
2
rocket
2
rocket
Submodule rocket updated: f08e60a165...49f633cd12
@ -256,8 +256,8 @@ class Top extends Module {
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nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
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val vic = ICacheConfig(128, 1)
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val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
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val rc = RocketConfiguration(tl, ic, dc,
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fpu = HAS_FPU
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val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
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val rc = RocketConfiguration(tl, ic, dc, fpu
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//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
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)
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@ -92,9 +92,8 @@ class FPGATop extends Module {
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val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4)
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val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
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val rc = RocketConfiguration(tl, ic, dc,
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fastMulDiv = false,
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fpu = false)
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val rc = RocketConfiguration(tl, ic, dc, fpu = None,
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fastMulDiv = false)
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val io = new FPGATopIO(htif_width)
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