Push rocket/hardfloat/chisel

chisel

@@ -1 +1 @@
-Subproject commit 56e8b23ff2d3336177f9e7d941f3d22200301ad0
+Subproject commit 25a33ba1d456294fe4ebc79fe95339a0d9d20e8a

csrc/emulator.cc

@@ -125,7 +125,7 @@ int main(int argc, char** argv)
     }
 
     if (log)
-      tile.print(stderr, stderr);
+      tile.print(stderr);
 
     if (vcd)
       tile.dump(vcdfile, trace_count);

hardfloat

@@ -1 +1 @@
-Subproject commit d1269259151b25e7a7a1ddc22bf85b92cd732118
+Subproject commit 39a08130d41ceb9e7f98fa7092fc38970009a460

rocket

@@ -1 +1 @@
-Subproject commit f08e60a16598deb32ddfb9eb9450463842555bab
+Subproject commit 49f633cd12de6e69479943d8089563edae7e03f5

src/main/scala/RocketChip.scala

@@ -256,8 +256,8 @@ class Top extends Module {
                         nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
   val vic = ICacheConfig(128, 1)
   val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
-  val rc = RocketConfiguration(tl, ic, dc,
-                               fpu = HAS_FPU
+  val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
+  val rc = RocketConfiguration(tl, ic, dc, fpu
                                //,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
                               )
 

src/main/scala/fpga.scala

@@ -92,9 +92,8 @@ class FPGATop extends Module {
 
   val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4)
   val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
-  val rc = RocketConfiguration(tl, ic, dc,
-                               fastMulDiv = false,
-                               fpu = false)
+  val rc = RocketConfiguration(tl, ic, dc, fpu = None,
+                               fastMulDiv = false)
 
   val io = new FPGATopIO(htif_width)