riscv/rocket-chip
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Reduce node count by avoiding elsewhen :-(

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This commit is contained in:
Andrew Waterman 2014-05-09 19:09:26 -07:00
parent 8dcc0cbb53
commit 0c13c00d08
1 changed files with 3 additions and 2 deletions
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5
rocket/src/main/scala/btb.scala
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@ -150,6 +150,9 @@ class BTB(implicit conf: BTBConfig) extends Module {
val waddr = Mux(updateHit, update.bits.prediction.bits.entry, nextRepl)
for (i <- 0 until conf.entries) {
when ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
idxValid(i) := false
}
when (waddr === i) {
idxValid(i) := updateValid
when (updateTarget) {
@ -161,8 +164,6 @@ class BTB(implicit conf: BTBConfig) extends Module {
useRAS(i) := update.bits.isReturn
isJump(i) := update.bits.isJump
}
}.elsewhen ((pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR) {
idxValid(i) := false
}
}