Add fclass.{s|d} instructions
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@ -232,6 +232,8 @@ object FDecode extends DecodeConstants
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FNMADD_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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FNMSUB_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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FNMSUB_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N),
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FCLASS_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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FCLASS_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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FMV_X_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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FMV_X_D-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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FCVT_W_S-> List(Y, Y,N,BR_N, N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N),
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@ -34,6 +34,7 @@ object FPConstants
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val FCMD_MIN = Bits("b011000")
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val FCMD_MAX = Bits("b011001")
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val FCMD_MFTX = Bits("b011100")
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val FCMD_CLASS = Bits("b011101")
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val FCMD_MXTF = Bits("b011110")
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val FCMD_MADD = Bits("b100100")
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val FCMD_MSUB = Bits("b100101")
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@ -91,6 +92,8 @@ class FPUDecoder extends Module
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FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,Y),
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FMV_X_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,Y),
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FMV_X_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,Y),
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FCLASS_S -> List(FCMD_CLASS, N,Y,N,N,Y,N,Y,N,N,Y),
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FCLASS_D -> List(FCMD_CLASS, N,Y,N,N,N,N,Y,N,N,Y),
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FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
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FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,Y),
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FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,Y),
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@ -203,7 +206,7 @@ class FPToInt extends Module
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when (io.in.bits.cmd === FCMD_STORE) {
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in.in1 := io.in.bits.in2
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}.otherwise {
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val doUpconvert = io.in.bits.single && io.in.bits.cmd != FCMD_MFTX
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val doUpconvert = io.in.bits.single && io.in.bits.cmd != FCMD_MFTX && io.in.bits.cmd != FCMD_CLASS
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in.in1 := Mux(doUpconvert, upconvert(io.in.bits.in1), io.in.bits.in1)
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in.in2 := Mux(doUpconvert, upconvert(io.in.bits.in2), io.in.bits.in2)
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}
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@ -236,6 +239,11 @@ class FPToInt extends Module
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io.out.bits.toint := d2i._1
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io.out.bits.exc := d2i._2
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}
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when (in.cmd === FCMD_CLASS) {
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val classify_s = hardfloat.recodedFloatNClassify(in.in1, 23, 9)
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val classify_d = hardfloat.recodedFloatNClassify(in.in1, 52, 12)
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io.out.bits.toint := Mux(in.single, classify_s, classify_d)
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}
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when (in.cmd === FCMD_EQ || in.cmd === FCMD_LT || in.cmd === FCMD_LE) {
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io.out.bits.toint := dcmp_out
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io.out.bits.exc := dcmp_exc
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@ -146,6 +146,8 @@ object Instructions {
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def FMAX_D = Bits("b1100101??????????000?????1010011")
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def FMV_X_S = Bits("b111000000000?????000?????1010011")
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def FMV_X_D = Bits("b111000100000?????000?????1010011")
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def FCLASS_S = Bits("b111010000000?????000?????1010011")
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def FCLASS_D = Bits("b111010100000?????000?????1010011")
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def FMV_S_X = Bits("b111100000000?????000?????1010011")
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def FMV_D_X = Bits("b111100100000?????000?????1010011")
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def FLW = Bits("b?????????????????010?????0000111")
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