riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
733 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
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Andrew Waterman 3ed8adf032 Add early out for MUL[W] (not MULH[[S]U])
2014-04-07 23:48:02 -07:00
rocket/src/main/scala Add early out for MUL[W] (not MULH[[S]U]) 2014-04-07 23:48:02 -07:00