riscv/rocket-chip
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Merge pull request #77 from ucb-bar/chisel3

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Preliminary Chisel 3 Support
This commit is contained in:
Andrew Waterman 2016-03-24 12:56:36 -07:00
commit d1639416cb
14 changed files with 68 additions and 76 deletions
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8
.gitmodules vendored
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@ -11,7 +11,7 @@
path = rocket
url = https://github.com/ucb-bar/rocket.git
[submodule "chisel"]
path = chisel
path = chisel2
url = https://github.com/ucb-bar/chisel.git
[submodule "hardfloat"]
path = hardfloat
@ -34,3 +34,9 @@
[submodule "torture"]
path = torture
url = https://github.com/ucb-bar/riscv-torture.git
[submodule "chisel3"]
path = chisel3
url = https://github.com/ucb-bar/chisel3.git
[submodule "firrtl"]
path = firrtl
url = https://github.com/ucb-bar/firrtl.git

2
.travis.yml
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@ -63,7 +63,7 @@ before_install:
- export CXX=g++-4.8 CC=gcc-4.8
script:
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default

8
Makefrag
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@ -8,10 +8,16 @@ PROJECT := rocketchip
CXX ?= g++
CXXFLAGS := -O1
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar
CHISEL_VERSION=2
SBT := CHISEL_SUBMODULE="chisel$(CHISEL_VERSION)" java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar
SHELL := /bin/bash
ifeq ($(CHISEL_VERSION),2)
CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
else
CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
endif
src_path = src/main/scala
default_submodules = . junctions uncore hardfloat rocket zscale groundtest context-dependent-environments

0
chisel → chisel2
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1
chisel3 Submodule

@ -0,0 +1 @@
Subproject commit e6ee1ddb79c219e313e530a029d8402274fbaebc

1
firrtl Submodule

@ -0,0 +1 @@
Subproject commit 8ae6ece99dfadb8d3dd25acc3549a975e3c40bbc

2
fsim/Makefile
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@ -15,7 +15,7 @@ mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
BACKEND ?= fpga
BACKEND ?= v
CONFIG ?= DefaultFPGAConfig
TB ?= rocketTestHarness

4
project/build.scala
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@ -8,14 +8,14 @@ object BuildSettings extends Build {
override lazy val settings = super.settings ++ Seq(
organization := "berkeley",
version := "1.2",
scalaVersion := "2.11.6",
scalaVersion := "2.11.7",
parallelExecution in Global := false,
traceLevel := 15,
scalacOptions ++= Seq("-deprecation","-unchecked"),
libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)
)
lazy val chisel = project
lazy val chisel = project in file(sys.env.getOrElse("CHISEL_SUBMODULE", "chisel2"))
lazy val cde = project in file("context-dependent-environments")
lazy val hardfloat = project.dependsOn(chisel)
lazy val junctions = project.dependsOn(chisel, cde)

17
regression/Makefile
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@ -16,6 +16,9 @@ ifeq ($(TORTURE_CONFIG),)
$(error Set TORTURE_CONFIG to the torture configuration to run)
endif
# The version of Chisel to use
CHISEL_VERSION ?= 2
# The top-level directory that contains rocket-chip
TOP ?= ..
@ -67,7 +70,7 @@ fsim-asm-tests: stamps/$(CONFIG)/fsim-asm-tests.stamp
fsim-bmark-tests: stamps/$(CONFIG)/fsim-bmark-tests.stamp
fsim-torture: stamps/$(CONFIG)/fsim-torture-$(TORTURE_CONFIG).stamp
submodule_names = chisel context-dependent-environments dramsim2 groundtest hardfloat junctions rocket torture uncore zscale $(ROCKETCHIP_ADDONS)
submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 groundtest hardfloat junctions rocket torture uncore zscale $(ROCKETCHIP_ADDONS)
# Checks out all the rocket-chip submodules
stamps/other-submodules.stamp:
@ -90,28 +93,28 @@ $(RISCV)/install.stamp:
# Builds the various simulators
stamps/$(CONFIG)/%-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-verilog.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) verilog
date > $@
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-verilog.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog
date > $@
stamps/$(CONFIG)/%-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-ndebug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV))
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-ndebug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION)
date > $@
stamps/$(CONFIG)/%-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
mkdir -p $(dir $@)
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-debug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) debug
+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-debug.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug
date > $@
# Runs tests on one of the simulators
stamps/$(CONFIG)/%-asm-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-asm-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-asm-tests
$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-asm-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-asm-tests
date > $@
stamps/$(CONFIG)/%-bmark-tests.stamp: stamps/$(CONFIG)/%-ndebug.stamp
mkdir -p $(dir $@)
$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-bmark-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) run-bmark-tests
$(MAKE) -C $(abspath $(TOP))/$(patsubst stamps/$(CONFIG)/%-bmark-tests.stamp,%,$@) CONFIG=$(CONFIG) RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) run-bmark-tests
date > $@
# The torture tests run subtly differently on the different targets, so they

55
src/main/scala/Backends.scala
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@ -1,55 +0,0 @@
// See LICENSE for license details.
package rocketchip
import Chisel._
import RocketChipBackend._
import scala.collection.mutable.HashMap
object RocketChipBackend {
val initMap = new HashMap[Module, Bool]()
}
class RocketChipBackend extends VerilogBackend
{
initMap.clear()
override def emitPortDef(m: MemAccess, idx: Int) = {
val res = new StringBuilder()
for (node <- m.mem.inputs) {
if(node.name.contains("init"))
res.append(" .init(" + node.name + "),\n")
}
(if (idx == 0) res.toString else "") + super.emitPortDef(m, idx)
}
def addMemPin(c: Module) = {
for (m <- Driver.components) {
m bfs { _ match {
case mem: Mem[_] if mem.seqRead =>
connectMemPin(m, mem)
case _ =>
} }
}
}
def connectInitPin(c: Module) {
initMap(c) = c.addPin(Bool(INPUT), "init")
if (!(initMap contains c.parent)) connectInitPin(c.parent)
initMap(c) := initMap(c.parent)
}
def connectMemPin(c: Module, mem: Mem[_]) {
if (!(initMap contains c)) connectInitPin(c)
mem.inputs += initMap(c)
}
def addTopLevelPin(c: Module) = {
initMap(c) = c.addPin(Bool(INPUT), "init")
}
transforms += addTopLevelPin
transforms += addMemPin
}
class Fame1RocketChipBackend extends RocketChipBackend with Fame1Transform

2
src/main/scala/RocketChip.scala
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@ -199,7 +199,7 @@ class Uncore(implicit val p: Parameters) extends Module
VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
} else {
htif.io.host.out <> io.host.out
io.host.out <> htif.io.host.out
htif.io.host.in <> io.host.in
}
}

2
uncore

@ -1 +1 @@
Subproject commit fa6be954e150e5a3d64e8221b6083c9feaed4268
Subproject commit 86f6845288d2d8feaa187331acd5a04d8cb1371e

2
vsim/Makefile
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@ -15,7 +15,7 @@ mem_gen = $(base_dir)/vsim/vlsi_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
BACKEND ?= rocketchip.RocketChipBackend
BACKEND ?= v
CONFIG ?= DefaultVLSIConfig
TB ?= rocketTestHarness

40
vsim/Makefrag-verilog
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@ -2,23 +2,53 @@
# Verilog Generation
#--------------------------------------------------------------------
$(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d : $(chisel_srcs)
ifeq ($(CHISEL_VERSION),2)
$(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d $(generated_dir)/$(MODEL).$(CONFIG).prm : $(chisel_srcs)
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(CHISEL_ARGS) --configDump --noInlineMem"
cd $(generated_dir) && \
if [ -a $(MODEL).$(CONFIG).conf ]; then \
$(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \
fi
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
else
FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
$(FIRRTL):
$(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build
# If I don't mark these as .SECONDARY then make will delete these internal
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
.SECONDARY: $(generated_dir)/MemDessert.$(CONFIG).fir
$(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(patsubst %.$(CONFIG).fir,%.fir,$@) $@
$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
$(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(generated_dir)/MemDessert.$(CONFIG).v
cat $(filter %.v,$^) \
| sed 's@MemDessert@memdessertMemDessert@g' \
| sed 's@Queue@memdessetQueue@g' \
> $@
endif
$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).prm
echo "\`ifndef CONST_VH" > $@
echo "\`define CONST_VH" >> $@
sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
echo "\`define TBVFRAG \"$(MODEL).$(CONFIG).tb.vfrag\"" >> $@
echo "\`endif // CONST_VH" >> $@
$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------