riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Fix nondeterminism

This commit is contained in:
Andrew Waterman 2014-03-15 17:35:30 -07:00
parent b6bf7cfe0c e4b56b5d0e
commit fcbbb275aa
3 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel

@ -1 +1 @@
Subproject commit ada8369a39e82890cd78b04db6661f426fb57df2
Subproject commit f8c3c094a685c1f5630bd2f61ba0434c2dfbd58f

3
project/build.scala
View File

@ -31,7 +31,8 @@ object BuildSettings extends Build {
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket)
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha)
lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel)
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")

2
rocket

@ -1 +1 @@
Subproject commit 76b583c8f3d279c4c9f0eea0947df25dec2ef5fb
Subproject commit ddb2db3f69ffabf9c985f76614603b4b0265c815