riscv/rocket-chip
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Fix nondeterminism

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Andrew Waterman
2014-03-15 17:35:30 -07:00
parent b6bf7cfe0c e4b56b5d0e
commit fcbbb275aa
3 changed files with 4 additions and 3 deletions
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2
chisel

Submodule chisel updated: ada8369a39...f8c3c094a6

3
project/build.scala
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@ -31,7 +31,8 @@ object BuildSettings extends Build {
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket)
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha)
lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel)
lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")

2
rocket

Submodule rocket updated: 76b583c8f3...ddb2db3f69