Fix Verilator VCD (#157)

chisel3

@@ -1 +1 @@
-Subproject commit c90be4ea06faf9a39c85f38e932d29fe63eb4b37
+Subproject commit 1b8f84859f2ac2d40085e6c31034dd598a5c6aad

csrc/emulator.cc

@@ -44,7 +44,6 @@ int main(int argc, char** argv)
   uint64_t max_cycles = -1;
   uint64_t start = 0;
   int ret = 0;
-  const char* vcd = NULL;
   const char* loadmem = NULL;
   FILE *vcdfile = NULL;
   bool dramsim2 = false;
@@ -55,9 +54,12 @@ int main(int argc, char** argv)
   for (int i = 1; i < argc; i++)
   {
     std::string arg = argv[i];
-    if (arg.substr(0, 2) == "-v")
-      vcd = argv[i]+2;
-    else if (arg.substr(0, 9) == "+memsize=")
+    if (arg.substr(0, 2) == "-v") {
+      const char* filename = argv[i]+2;
+      vcdfile = strcmp(filename, "-") == 0 ? stdout : fopen(filename, "w");
+      if (!vcdfile)
+        abort();
+    } else if (arg.substr(0, 9) == "+memsize=")
       memsz_mb = atoll(argv[i]+9);
     else if (arg.substr(0, 2) == "-s")
       random_seed = atoi(argv[i]+2);
@@ -75,38 +77,26 @@ int main(int argc, char** argv)
       print_cycles = true;
   }
 
-  const int disasm_len = 24;
+  srand(random_seed);
+  srand48(random_seed);
 
 #ifndef VERILATOR
-  if (vcd)
-  {
-    // Create a VCD file
-    vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
-    assert(vcdfile);
-    fprintf(vcdfile, "$scope module Testbench $end\n");
-    fprintf(vcdfile, "$var reg %d NDISASM_WB wb_instruction $end\n", disasm_len*8);
-    fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
-    fprintf(vcdfile, "$upscope $end\n");
-  }
-
-  // The chisel generated code
   Top_t tile;
   tile.init(random_seed);
 #else
+  Verilated::randReset(2);
   VTop tile;
+
 #if VM_TRACE
-  VerilatedVcdC *tfp = NULL;
-  if (vcd) {
-    tfp = new VerilatedVcdC;
-    Verilated::traceEverOn(true); // Verilator must compute traced signals
-    VL_PRINTF("Enabling waves... (%s)\n", vcd);
-    tile.trace(tfp, 99);  // Trace 99 levels of hierarchy
-    tfp->open(vcd); // Open the dump file
+  Verilated::traceEverOn(true); // Verilator must compute traced signals
+  std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
+  std::unique_ptr<VerilatedVcdC> tfp(new VerilatedVcdC(vcdfd.get()));
+  if (vcdfile) {
+    tile.trace(tfp.get(), 99);  // Trace 99 levels of hierarchy
+    tfp->open("");
   }
 #endif
 #endif
-  srand(random_seed);
-
 
   uint64_t mem_width = MEM_DATA_BITS / 8;
 
@@ -266,7 +256,7 @@ int main(int argc, char** argv)
       tile.print(stderr);
 
     // make sure we dump on cycle 0 to get dump_init
-    if (vcd && (trace_count == 0 || trace_count >= start))
+    if (vcdfile && (trace_count == 0 || trace_count >= start))
       tile.dump(vcdfile, trace_count);
 
     tile.clock_hi(LIT<1>(0));
@@ -281,15 +271,16 @@ int main(int argc, char** argv)
     trace_count++;
   }
 
-#ifndef VERILATOR
-  if (vcd) fclose(vcdfile);
-#else
+#ifdef VERILATOR
 #if VM_TRACE
-  if (tfp) tfp->close();
-  delete tfp;
+  if (tfp)
+    tfp->close();
 #endif
 #endif
 
+  if (vcdfile)
+    fclose(vcdfile);
+
   if (dtm->exit_code())
   {
     fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count);

csrc/verilator.h

@@ -1,6 +1,28 @@
 #ifndef _ROCKET_VERILATOR_H
 #define _ROCKET_VERILATOR_H
 
+#include "verilated_vcd_c.h"
+#include <stdlib.h>
+#include <stdio.h>
+
 extern bool verbose;
 
+class VerilatedVcdFILE : public VerilatedVcdFile {
+ public:
+  VerilatedVcdFILE(FILE* file) : file(file) {}
+  ~VerilatedVcdFILE() {}
+  bool open(const string& name) override {
+    // file should already be open
+    return file != NULL;
+  }
+  void close() override {
+    // file should be closed elsewhere
+  }
+  ssize_t write(const char* bufp, ssize_t len) override {
+    return fwrite(bufp, 1, len, file);
+  }
+ private:
+  FILE* file;
+};
+
 #endif

emulator/Makefrag-verilator

@@ -55,24 +55,19 @@ VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\)
 	-Wno-STMTDLY --x-assign unique \
   -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
+headers = $(wildcard $(base_dir)/csrc/*.h)
 
 model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
 model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
 
-$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header)
-	$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir) -c -o $@ $<
-
-$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header_debug)
-	$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -c -o $@ $<
-
-$(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header) $(INSTALLED_VERILATOR)
+$(emu): $(verilog) $(cppfiles) $(headers) libdramsim.a $(consts_header) $(INSTALLED_VERILATOR)
 	mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
 	$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
 
-$(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
+$(emu_debug): $(verilog_debug) $(cppfiles) $(headers) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
 	mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG)  --trace \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \

groundtest

@@ -1 +1 @@
-Subproject commit 6d65b7f0dd5bc279d65783aa11c664345107a0b9
+Subproject commit f5d1a1b27bc369b9fed9c9f5fb3649f9e94edf6b

rocket

@@ -1 +1 @@
-Subproject commit 5c87faad33ab949af5d8daaa3b3439ceecfd7b83
+Subproject commit 65c16780535f702d7cb1f20d91146e196a593f9f