riscv/rocket-chip
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Merge pull request #18 from jackkoenig/master

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Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
This commit is contained in:
Andrew Waterman 2015-11-08 22:38:01 -08:00
commit 59ca373146
1 changed files with 2 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -751,6 +751,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s1_clk_en = Reg(Bool())
val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
val s2_killed = Reg(next=s1_valid && io.cpu.req.bits.kill)
val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
val s2_recycle = Wire(Bool())
@ -1053,7 +1054,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid
val cache_pass = s2_valid || s2_replay
val cache_pass = s2_valid || s2_killed || s2_replay
mshrs.io.resp.ready := !cache_pass
io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)