riscv/rocket-chip
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Remove vestigial control signals

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This commit is contained in:
Andrew Waterman 2014-06-03 10:28:42 -07:00
parent 04593d433e
commit 3828c628c3
1 changed files with 0 additions and 6 deletions
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6
rocket/src/main/scala/ctrl.scala
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@ -311,12 +311,6 @@ class Control(implicit conf: RocketConfiguration) extends Module
val dpath = new CtrlDpathIO
val imem = new CPUFrontendIO()(conf.icache)
val dmem = new HellaCacheIO()(conf.dcache)
val dtlb_val = Bool(OUTPUT)
val dtlb_kill = Bool(OUTPUT)
val dtlb_rdy = Bool(INPUT)
val dtlb_miss = Bool(INPUT)
val xcpt_dtlb_ld = Bool(INPUT)
val xcpt_dtlb_st = Bool(INPUT)
val fpu = new CtrlFPUIO
val rocc = new RoCCInterface().flip
}