Add early out for MUL[W] (not MULH[[S]U])
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@ -91,10 +91,16 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke
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val mpcand = divisor.toSInt
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val prod = mplier(mulUnroll-1,0) * mpcand + accum
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val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
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remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
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val eOutMask = (SInt(BigInt(-1) << mulw) >> (count * mulUnroll)(log2Up(mulw)-1,0))(mulw-1,0)
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val eOut = Bool(earlyOut) && count != mulw/mulUnroll-1 && count != 0 &&
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!isHi && (mplier & ~eOutMask) === UInt(0)
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val eOutRes = (mulReg >> (mulw - count * mulUnroll)(log2Up(mulw)-1,0))
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val nextMulReg1 = Cat(nextMulReg(2*mulw,mulw), Mux(eOut, eOutRes, nextMulReg)(mulw-1,0))
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remainder := Cat(nextMulReg1 >> w, Bool(false), nextMulReg1(w-1,0)).toSInt
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count := count + 1
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when (count === mulw/mulUnroll-1) {
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when (eOut || count === mulw/mulUnroll-1) {
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state := Mux(isHi, s_move_rem, s_done)
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}
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}
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