Add 16 microarchitectural counters
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2c2b3a7678
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@ -192,6 +192,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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pcr.io <> io.fpu
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pcr.io.pc := wb_reg_pc
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io.ctrl.csr_replay := pcr.io.replay
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pcr.io.uarch_counters.foreach(_ := Bool(false))
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io.ptw.ptbr := pcr.io.ptbr
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io.ptw.invalidate := pcr.io.fatc
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@ -99,6 +99,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val evec = UInt(OUTPUT, VADDR_BITS+1)
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val exception = Bool(INPUT)
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val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
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val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth)))
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val cause = UInt(INPUT, conf.xprlen)
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val badvaddr_wen = Bool(INPUT)
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val pc = UInt(INPUT, VADDR_BITS+1)
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@ -124,6 +125,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val reg_status = Reg(new Status) // reset down below
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val reg_time = WideCounter(conf.xprlen)
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val reg_instret = WideCounter(conf.xprlen, io.retire)
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val reg_uarch_counters = io.uarch_counters.map(WideCounter(conf.xprlen, _))
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val reg_fflags = Reg(UInt(width = 5))
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val reg_frm = Reg(UInt(width = 3))
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@ -209,7 +211,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val read_impl = Bits(2)
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val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
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val read_mapping = Map[Int,Bits](
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val read_mapping = collection.mutable.Map[Int,Bits](
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CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)),
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CSRs.frm -> (if (conf.fpu) reg_frm else UInt(0)),
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CSRs.fcsr -> (if (conf.fpu) Cat(reg_frm, reg_fflags) else UInt(0)),
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@ -236,6 +238,9 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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CSRs.tohost -> reg_tohost,
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CSRs.fromhost -> reg_fromhost)
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for (i <- 0 until reg_uarch_counters.size)
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read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
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io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
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io.fcsr_rm := reg_frm
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@ -219,6 +219,22 @@ object CSRs {
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val fflags = 0x1
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val frm = 0x2
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val fcsr = 0x3
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val uarch0 = 0x80
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val uarch1 = 0x81
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val uarch2 = 0x82
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val uarch3 = 0x83
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val uarch4 = 0x84
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val uarch5 = 0x85
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val uarch6 = 0x86
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val uarch7 = 0x87
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val uarch8 = 0x88
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val uarch9 = 0x89
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val uarch10 = 0x8a
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val uarch11 = 0x8b
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val uarch12 = 0x8c
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val uarch13 = 0x8d
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val uarch14 = 0x8e
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val uarch15 = 0x8f
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val sup0 = 0x500
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val sup1 = 0x501
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val epc = 0x502
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@ -247,6 +263,22 @@ object CSRs {
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res += fflags
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res += frm
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res += fcsr
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res += uarch0
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res += uarch1
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res += uarch2
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res += uarch3
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res += uarch4
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res += uarch5
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res += uarch6
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res += uarch7
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res += uarch8
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res += uarch9
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res += uarch10
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res += uarch11
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res += uarch12
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res += uarch13
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res += uarch14
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res += uarch15
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res += sup0
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res += sup1
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res += epc
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