Merge pull request #70 from ucb-bar/add-rv32-support
Add RV32 test/configuration options
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commit
648437e7cb
@ -149,8 +149,11 @@ class DefaultConfig extends Config (
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case OuterTLId => "L2toMC" })))
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//Tile Constants
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case BuildTiles => {
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TestGeneration.addSuites(rv64i.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
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val (rvi, rvu) =
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if (site(XLen) == 64) (rv64i, rv64u)
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else (rv32i, rv32u)
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TestGeneration.addSuites(rvi.map(_("p")))
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TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rvu.map(_(env))))
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TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
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List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
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Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
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@ -352,6 +355,13 @@ class WithZscale extends Config(
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}
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)
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class WithRV32 extends Config(
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(pname,site,here) => pname match {
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case XLen => 32
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case UseFPU => false
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}
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)
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class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
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class FPGAConfig extends Config (
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@ -380,6 +390,8 @@ class SmallConfig extends Config (
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class DefaultFPGASmallConfig extends Config(new SmallConfig ++ new DefaultFPGAConfig)
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class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
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class ExampleSmallConfig extends Config(new SmallConfig ++ new DefaultConfig)
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class DualBankConfig extends Config(new With2BanksPerMemChannel ++ new DefaultConfig)
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@ -137,6 +137,15 @@ object DefaultTestSuites {
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val rv32uaNames = LinkedHashSet("amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w")
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val rv32ua = new AssemblyTestSuite("rv32ua", "rv32ui", rv32uaNames)(_)
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val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
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val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
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val rv32miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall", "timer")
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val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
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val rv32u = List(rv32ui, rv32um, rv32ua)
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val rv32i = List(rv32ui, rv32si, rv32mi)
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val rv64uiNames = LinkedHashSet("addw", "addiw", "ld", "lwu", "sd", "slliw", "sllw", "sltiu", "sltu", "sraiw", "sraw", "srliw", "srlw", "subw")
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val rv64ui = new AssemblyTestSuite("rv64ui", "rv64ui", rv32uiNames ++ rv64uiNames)(_)
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@ -150,10 +159,10 @@ object DefaultTestSuites {
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val rv64uf = new AssemblyTestSuite("rv64uf", "rv64uf", rv64ufNames)(_)
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val rv64ufNoDiv = new AssemblyTestSuite("rv64uf", "rv64uf", rv64ufNames - "fdiv")(_)
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val rv64siNames = LinkedHashSet("csr", "illegal", "ma_fetch", "ma_addr", "scall", "sbreak", "wfi")
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val rv64siNames = rv32siNames
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val rv64si = new AssemblyTestSuite("rv64si", "rv64si", rv64siNames)(_)
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val rv64miNames = LinkedHashSet("csr", "mcsr", "wfi", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall", "timer")
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val rv64miNames = rv32miNames
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val rv64mi = new AssemblyTestSuite("rv64mi", "rv64mi", rv64miNames)(_)
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// TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",
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