Ignore rocc interrupt line when no rocc is present
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@ -132,6 +132,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val r_irq_timer = Reg(init=Bool(false))
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val r_irq_ipi = Reg(init=Bool(true))
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val irq_rocc = Bool(!conf.rocc.isEmpty) && io.rocc.interrupt
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val cpu_req_valid = io.rw.cmd != CSR.N
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val host_pcr_req_valid = Reg(Bool()) // don't reset
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@ -171,8 +172,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
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val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
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io.status := reg_status
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io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
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Bool(false), io.rocc.interrupt, Bool(false), Bool(false))
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io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
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Bool(false), irq_rocc, Bool(false), Bool(false))
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io.fatc := wen && decoded_addr(CSRs.fatc)
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io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
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io.ptbr := reg_ptbr
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