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riscv
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rocket-chip
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364a6de2145dd3e81cd432cf31fa56bb177eef3f
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Andrew Waterman
364a6de214
Use Mem instead of Vec[Reg]
2014-05-18 19:26:35 -07:00
uncore
Use Mem instead of Vec[Reg]
2014-05-18 19:26:35 -07:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%