riscv/rocket-chip
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Update PLIC/PRCI address map (#124)

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This commit is contained in:
Andrew Waterman 2016-06-06 04:51:55 -07:00
parent ece3ab9c3d
commit d24c87f8ba
4 changed files with 15 additions and 17 deletions
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2
riscv-tools

@ -1 +1 @@
Subproject commit dddbdec89bb045a3cd134f4776619097c838f20a
Subproject commit 0a12a54524dba399cacc2955dc3489d8cda58740

11
src/main/scala/Configs.scala
View File

@ -28,9 +28,8 @@ class BaseConfig extends Config (
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
entries += AddrMapEntry("rtc", MemSize(4096, MemAttr(AddrMapProt.RW)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 4096 * 1024, MemAttr(AddrMapProt.RW)))
for (i <- 0 until site(NTiles))
entries += AddrMapEntry(s"prci$i", MemSize(4096, MemAttr(AddrMapProt.RW)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
new AddrMap(entries)
}
lazy val globalAddrMap = {
@ -53,7 +52,8 @@ class BaseConfig extends Config (
}
def makeConfigString() = {
val addrMap = globalAddrMap
val plicAddr = addrMap(s"io:int:plic").start
val plicAddr = addrMap("io:int:plic").start
val prciAddr = addrMap("io:int:prci").start
val plicInfo = site(PLICKey)
val xLen = site(XLen)
val res = new StringBuilder
@ -79,12 +79,11 @@ class BaseConfig extends Config (
for (i <- 0 until site(NTiles)) {
val isa = s"rv${site(XLen)}im${if (site(UseAtomics)) "a" else ""}${if (site(UseFPU)) "fd" else ""}"
val timecmpAddr = addrMap("io:int:rtc").start + 8*(i+1)
val prciAddr = addrMap(s"io:int:prci$i").start
res append s" $i {\n"
res append " 0 {\n"
res append s" isa $isa;\n"
res append s" timecmp 0x${timecmpAddr.toString(16)};\n"
res append s" ipi 0x${prciAddr.toString(16)};\n"
res append s" ipi 0x${(prciAddr + 4*i).toString(16)};\n"
res append s" plic {\n"
res append s" m {\n"
res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"

17
src/main/scala/RocketChip.scala
View File

@ -211,18 +211,17 @@ class Uncore(implicit val p: Parameters) extends Module
debugModule.io.tl <> mmioNetwork.port("int:debug")
debugModule.io.db <> io.debugBus
val prci = Module(new PRCI)
prci.io.tl <> mmioNetwork.port("int:prci")
io.prci := prci.io.tiles
for (i <- 0 until nTiles) {
val prci = Module(new PRCI)
prci.io.tl <> mmioNetwork.port(s"int:prci$i")
prci.io.id := UInt(i)
prci.io.interrupts.mtip := rtc.io.irqs(i)
prci.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
prci.io.interrupts(i).mtip := rtc.io.irqs(i)
prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
if (p(UseVM))
prci.io.interrupts.seip := plic.io.harts(plic.cfg.context(i, 'S'))
prci.io.interrupts.debug := debugModule.io.debugInterrupts(i)
prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
io.prci(i) := prci.io.tile
io.prci(i).reset := Reg(next=Reg(next=htif.io.cpu(i).reset)) // TODO
}

2
uncore

@ -1 +1 @@
Subproject commit 65db9e3eaa174bce72346770d91fe0592f964cb8
Subproject commit efc19629b3c7e8668a72323ca3cc8514596e5e31