Merge branch 'master' into incisive-fixes
This commit is contained in:
commit
9326cfd64a
@ -42,7 +42,7 @@ branches:
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except:
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- hwacha
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- boom
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- hurricane
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- /^hurricane.*$/
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before_install:
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- export CXX=g++-4.8 CC=gcc-4.8
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2
firrtl
2
firrtl
@ -1 +1 @@
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Subproject commit 8b12dcbb76896a19f95dc4da19b3b8c74c1ddda3
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Subproject commit bcf73fb70969e5629a693c18f1f2ee7b37f14a76
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@ -129,7 +129,7 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
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io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
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io.resp.valid := s1_hit
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case 2 =>
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val s2_hit = RegEnable(s1_hit, !stall)
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val s2_hit = RegEnable(s1_hit, Bool(false), !stall)
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val s2_tag_hit = RegEnable(s1_tag_hit, !stall)
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val s2_dout = RegEnable(s1_dout, !stall)
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io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)
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@ -143,8 +143,8 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
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val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
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// Indirection variables for inputs and outputs; makes transformation application easier
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val (in_ar, ar_last, _) = fragment(in.ar, readSizes1)
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val (in_aw, aw_last, w_beats) = fragment(in.aw, writeSizes1)
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val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
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val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
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val in_w = in.w
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val in_r = in.r
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val in_b = in.b
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@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.prm $(generated_dir)/%.d: $(chisel_src
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$(generated_dir)/$(long_name).v $(generated_dir)/$(long_name).conf : $(firrtl) $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --inferRW $(MODEL) --replSeqMem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
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$(FIRRTL) -i $< -o $(generated_dir)/$(long_name).v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$(long_name).conf
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
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cd $(generated_dir) && \
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