riscv/rocket-chip
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Make uarch counters read-only

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This commit is contained in:
Andrew Waterman 2014-02-06 01:48:56 -08:00
parent f021213b1d
commit e7a726fbac
1 changed files with 32 additions and 32 deletions
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64
rocket/src/main/scala/instructions.scala
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@ -219,22 +219,6 @@ object CSRs {
val fflags = 0x1
val frm = 0x2
val fcsr = 0x3
val uarch0 = 0x80
val uarch1 = 0x81
val uarch2 = 0x82
val uarch3 = 0x83
val uarch4 = 0x84
val uarch5 = 0x85
val uarch6 = 0x86
val uarch7 = 0x87
val uarch8 = 0x88
val uarch9 = 0x89
val uarch10 = 0x8a
val uarch11 = 0x8b
val uarch12 = 0x8c
val uarch13 = 0x8d
val uarch14 = 0x8e
val uarch15 = 0x8f
val sup0 = 0x500
val sup1 = 0x501
val epc = 0x502
@ -258,27 +242,27 @@ object CSRs {
val cycle = 0xc00
val time = 0xc01
val instret = 0xc02
val uarch0 = 0xc10
val uarch1 = 0xc11
val uarch2 = 0xc12
val uarch3 = 0xc13
val uarch4 = 0xc14
val uarch5 = 0xc15
val uarch6 = 0xc16
val uarch7 = 0xc17
val uarch8 = 0xc18
val uarch9 = 0xc19
val uarch10 = 0xc1a
val uarch11 = 0xc1b
val uarch12 = 0xc1c
val uarch13 = 0xc1d
val uarch14 = 0xc1e
val uarch15 = 0xc1f
val all = {
val res = collection.mutable.ArrayBuffer[Int]()
res += fflags
res += frm
res += fcsr
res += uarch0
res += uarch1
res += uarch2
res += uarch3
res += uarch4
res += uarch5
res += uarch6
res += uarch7
res += uarch8
res += uarch9
res += uarch10
res += uarch11
res += uarch12
res += uarch13
res += uarch14
res += uarch15
res += sup0
res += sup1
res += epc
@ -302,6 +286,22 @@ object CSRs {
res += cycle
res += time
res += instret
res += uarch0
res += uarch1
res += uarch2
res += uarch3
res += uarch4
res += uarch5
res += uarch6
res += uarch7
res += uarch8
res += uarch9
res += uarch10
res += uarch11
res += uarch12
res += uarch13
res += uarch14
res += uarch15
res.toArray
}
}