Andrew Waterman 137b77d780 Merge pull request #4 from ucb-bar/chisel3 ...

Work around Chisel3's lack of 0-width wires

2016-03-15 17:30:34 -07:00

groundtest

Work around Chisel3's lack of 0-width wires

2016-03-14 22:50:37 -07:00

S

Description

Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

13 MiB

Languages

Scala 93.1%

C++ 2.1%

Python 2%

Makefile 1.2%

Verilog 0.8%

Other 0.7%