riscv/rocket-chip
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Merge branch 'master' into test-harness-fixes

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Andrew Waterman
2016-08-19 22:53:12 -07:00
committed by GitHub
parent 96a868d388 22ffe36258
commit b7181ba49b
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/coreplex/Coreplex.scala
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@@ -193,7 +193,9 @@ class DefaultOuterMemorySystem(implicit p: Parameters) extends OuterMemorySystem
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMMIO"
})))
io.mmio <> mmioManager.io.outer
io.mmio.acquire <> Queue(mmioManager.io.outer.acquire, 1)
mmioManager.io.outer.grant <> Queue(io.mmio.grant, 1)
// Wire the tiles to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side