riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. Terpstra 69b3de92a8 tilelink2: decouple BaseNode from TileLink bus (so it can be reused) 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra c785375276 tilelink2: use 'connect' instead of TL-specific 'tl' to connect nodes 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 05221d7073 tilelink2: rename Bases.scala to LazyModule.scala 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 8d54ae8508 tilelink2: move TL-specific stuff out of the LazyModule base classes 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra f99a3dbec7 tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 5b31fb81fe tilelink2: IDNode needs to be specialized for output vs. input passthrough 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra eac4d44131 tilelink2: don't apply HintHandler to B=>C by default 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra cc8112d02e tilelink2: pass E through the HintHandler 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra a72f7115ae tilelink2: optimize support testing circuits 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra f0cfd81820 tilelink2: add an adapter to add support for Hints to devices 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 5f6ca0bd0d tilelink2: rename wmask => mask since it also applies to reads 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra 7347b0c4dd tilelink2: TLLegacy converts from legacy TileLink to TileLink2 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra fa472e38fb tilelink2: monitor error line legality 2016-09-05 20:58:39 -07:00
Wesley W. Terpstra edb17d1e34 tilelink2: document allowed (and required) response messages 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra ec1f901a38 tilelink2: move error from type into Bundle and add HintAck 
We need Grant with errors too.
We also want to match response type to request type more easily.
 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 534d7f6eb6 tilelink2: implement SRAM manager 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 32894a8e20 tilelink2: transfers must never exceed 4kB 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra dd27a60daa tilelink2: use consistent in/out ports for TLSimpleFactories 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 1a87eef3e2 tilelink2: add atomic message types 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 5f7711a0c0 tilelink2: add an intermediate type for simple factories 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 967d8f108c tilelink2: support ready-valid enqueue+dequeue on register fields 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 77cf186cf0 tilelink2: make bundle parameterization reusable 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 594850eaae tilelink2: assert-fail on something more user understandable 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra dc1164a996 tilelink2: defer bundle construction until after Module base class instantiated 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 18e149098a tilelink2: connect abstract register-based modules to TileLink 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 917a9c8e5d tilelink2: forward declarations for message constructors 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 4649c42f50 tilelink2: use a new type in the signature of null-parameter Bundle methods 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 0ff33a31a4 tilelink2: add a stub SRAM manager 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra a87c2d13e2 tilelink2: include an abstract definition for register mapped devices 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 3a441d853f tilelink2: clarify that fifoId only applies to accesses (not hints) 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra 4b99bd3be1 tilelink2: mask out unnecessary address bits 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra e24ba61754 tilelink2: distinguish two levels of uncacheability 2016-09-05 20:58:38 -07:00
Wesley W. Terpstra e506309998 tilelink2: prototype crossbar implementation 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 34f65938b6 tilelink2: add a TLBundle constructor 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 1cd85ff050 tilelink2: add some bundle introspection to scaffold the xbar 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 9c62f5d9c1 tilelink2: shave off a few more firrtl monitor lines 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra af29595979 tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra d7e839280f tilelink2: include legal message monitor 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 492a38aedc tilelink2: only accesses can have errors (release must make forward progress) 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 6599bcb77b tilelink2: statically check Operations are remotely plausible 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 8cff45f254 tilelink2: use byte-aligned addressing 
This makes it possible to fully validate user input in a monitor.
We will override the lower bits with constant 0s in the TL connect.
 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 45e152e97e tilelink2: include Operation constructors 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 5b10c1a328 tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3) 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 8592cbf0e3 tilelink2: Message and Permisison types from Henry 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 9a460322da tilelink2: add synthesizable test methods for Parameters 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 7328b55abd tilelink2: first cut at parameterization 2016-09-05 20:58:37 -07:00
Wesley W. Terpstra 11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter 2016-07-22 14:51:05 -07:00
Wesley W. TerpstraandHoward Mao a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations 2016-07-22 14:48:22 -07:00
Wesley W. TerpstraandHoward Mao 9ae23f18bd rocket: support asynchronous external busses 2016-07-19 14:52:56 -07:00
Wesley W. TerpstraandHoward Mao fa8317fec1 debug: add clock crossing primitives 2016-07-19 14:52:43 -07:00
Wesley W. TerpstraandHoward Mao eeae74e3fc nasti: include convenient clock crossing helpers 2016-07-13 14:20:25 -07:00
Wesley W. TerpstraandHoward Mao c33c0944be crossing: first clock crossing, the handshaker 2016-07-13 14:20:25 -07:00
Wesley W. Terpstra 46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra 8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Wesley W. TerpstraandHoward Mao 39bee5198d Nasti Puts: decode wmask to determine addr_byte() and op_size() 
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
 2016-07-01 16:49:32 -07:00
Wesley W. TerpstraandHoward Mao 70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Wesley W. TerpstraandHoward Mao 3e51a8bb7a submodules: include new ComparatorTile 2016-06-09 15:43:13 -07:00
Wesley W. TerpstraandHoward Mao 5562241a50 comparator: a new TileLink stress-tester 2016-06-09 14:02:35 -07:00
Wesley W. TerpstraandHenry Cook a1ebc73477 tilelink: don't accidentally make a malformed union 
Closes #55
 2016-06-09 10:44:00 -07:00
Wesley W. TerpstraandHenry Cook 31b72625aa ahb: allow no-ops to progress also when a slave is !hready 2016-06-09 10:41:12 -07:00
Wesley W. TerpstraandHenry Cook 7014eef339 ahb: fix bugs found using comparatortest 2016-06-09 10:41:11 -07:00
Wesley W. Terpstra ed9fcea7f8 hasti: correct fix to locking 2016-06-08 16:28:30 -07:00
Wesley W. Terpstra ad4e4f19be Revert "Don't rely on Mux1H output when no inputs are hot" 
This reverts commit b912b7cd1263d7f3b63e6fcb052d9d7493d1b970.
 2016-06-08 16:28:30 -07:00
Wesley W. Terpstra 3393d4362b hasti: fix test SRAM depth 2016-06-08 16:28:30 -07:00
Wesley W. Terpstra 324cabc494 tilelink: wmask was double the width it should be 
When amo_offset = UInt(0), UIntToOH(amo_offset) = "b01", not b"1".
This meant that the amo wmask was double wide, making wmask() fat.
 2016-06-07 14:04:01 -07:00
Wesley W. TerpstraandAndrew Waterman 5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. TerpstraandAndrew Waterman ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. TerpstraandAndrew Waterman 3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. TerpstraandAndrew Waterman d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. TerpstraandAndrew Waterman 2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. TerpstraandAndrew Waterman 2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. TerpstraandAndrew Waterman 31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. TerpstraandAndrew Waterman 7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. TerpstraandAndrew Waterman f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Wesley W. TerpstraandAndrew Waterman 11b3cee07a Ahb tweaks (#50) 
* ahb: handle tlDataBytes==1 and tlDataBeats==1 gracefully

I only now learned that chisel does not handle 0-width wires properly
and that log2Up and log2Ceil differ on 1. Fix-up code to handle this.

* ahb: optionally disable atomics => optimize to nothing

Trust the compiler the compiler to optimize away unused logic.
 2016-06-01 16:42:39 -07:00
Wesley W. TerpstraandAndrew Waterman 695be2f0ae hasti: work-around unsupported 0-width signals 2016-06-01 16:38:49 -07:00
Wesley W. TerpstraandAndrew Waterman 976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Wesley W. TerpstraandAndrew Waterman 7f1792cba3 ahb: backport bridge to chisel2 
Closes #47
 2016-05-25 13:40:24 -07:00
Wesley W. TerpstraandAndrew Waterman 1c8745dfd2 ahb: backport to chisel2 
Merges #16
 2016-05-25 12:11:26 -07:00
Wesley W. TerpstraandAndrew Waterman da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Wesley W. TerpstraandAndrew Waterman e19c5e5d2c IOMSHR: support atomic operations 2016-05-24 15:00:50 -07:00
Wesley W. Terpstra a012341d96 ahb: TileLink => AHB bridge, including atomics and bursts 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra ace9362d81 ahb: amoalu does not need so many parameters! (i want to reuse it) 2016-05-24 14:58:27 -07:00
Wesley W. Terpstra b921bae107 ahb: eliminate trait abused for constants 2016-05-24 14:20:45 -07:00
Wesley W. Terpstra 200c69c106 ahb: support hmastlock acquistion of crossbar 2016-05-24 14:20:45 -07:00
Wesley W. Terpstra e1e8eda419 ahb: add a test SRAM 2016-05-24 14:20:42 -07:00
Wesley W. Terpstra 1db40687c6 ahb: eliminate now-unnecesary non-standard hreadyin 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra 15cad8414d ahb: put signals in the order they appear in signal traces in the spec 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra f30f8d9f79 ahb: reduce obsolete degenerate cases of a crossbar 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra 0368b6db6b ahb: replace defective crossbar with a functional one 
The previous crossbar had the following bugs:
  1. a bursting master could be preempted
     the AHB-lite spec requires a slave receive the entire burst

  2. a waited master could be replaced
     the AHB-lite spec requires haddr/etc to remain unchanged

  3. hmastlock did no ensure exclusive access
     atomic operations could be pre-empted
 2016-05-24 14:14:22 -07:00
Wesley W. Terpstra 2b37f37335 ahb: helper methods 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra ef2aae26a8 ahb: rename hreadyout to standard hready, mark hreadyin for death 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra 2f8a77f27a ahb: include all AHB-lite constants 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra 7896c4157e ahb: parameterize poci 2016-05-24 14:14:21 -07:00
Wesley W. Terpstra 93447eb274 ahb: make hasti parameters location sensitive 2016-05-24 14:14:17 -07:00
Wesley W. Terpstra 00d31dc5c5 bram: use new hasti definitions 2016-05-24 13:35:16 -07:00