bram: don't deal with multibeat; rely on the fragmenter
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@ -11,78 +11,53 @@ class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
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with HasTileLinkParameters {
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val io = new ClientUncachedTileLinkIO().flip
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val bram = SeqMem(depth, Bits(width = tlDataBits))
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// For TL2:
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// supportsAcquire = false
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// supportsMultibeat = false
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// supportsHint = false
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// supportsAtomic = false
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val fire_acq = io.acquire.fire()
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val fire_gnt = io.grant.fire()
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// Timing-wise, we assume the input is coming out of registers
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// since you probably needed a TileLinkFragmenter infront of us
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val state_getblk = Reg(init = Bool(false))
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val state_putblk = Reg(init = Bool(false))
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val state_init = !(state_getblk || state_putblk)
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// Thus, only one pipeline stage: the grant result
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val g_valid = RegInit(Bool(false))
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val g_bits = Reg(new Grant)
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private def last(acq: AcquireMetadata) =
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(acq.addr_beat === UInt(tlDataBeats-1))
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// Just pass the pipeline straight through
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io.grant.valid := g_valid
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io.grant.bits := g_bits
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io.acquire.ready := !g_valid || io.grant.ready
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val s0_acq = io.acquire.bits
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val s0_last = last(s0_acq)
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val acq_get = io.acquire.bits.isBuiltInType(Acquire.getType)
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val acq_put = io.acquire.bits.isBuiltInType(Acquire.putType)
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val acq_addr = Cat(io.acquire.bits.addr_block, io.acquire.bits.addr_beat)
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val s1_acq = RegEnable(s0_acq, fire_acq)
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val s1_last = last(s1_acq)
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val bram = Mem(depth, Bits(width = tlDataBits))
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val (is_get :: is_getblk :: is_put :: is_putblk :: Nil) =
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Seq(Acquire.getType, Acquire.getBlockType,
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Acquire.putType, Acquire.putBlockType).map(s0_acq.isBuiltInType _)
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val ren = acq_get && io.acquire.fire()
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val wen = acq_put && io.acquire.fire()
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val is_read = is_get || is_getblk
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val is_write = is_put || is_putblk
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val ren_getblk = state_getblk && !s1_last
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when (io.grant.fire()) {
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g_valid := Bool(false)
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}
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val s0_valid = (fire_acq && (!is_putblk || s0_last)) || ren_getblk
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val s1_valid = RegNext(s0_valid, Bool(false))
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when (io.acquire.fire()) {
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g_valid := Bool(true)
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g_bits := Grant(
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is_builtin_type = Bool(true),
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g_type = io.acquire.bits.getBuiltInGrantType(),
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client_xact_id = io.acquire.bits.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = io.acquire.bits.addr_beat,
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data = UInt(0))
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}
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val ren = (fire_acq && is_read) || ren_getblk
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val wen = (fire_acq && is_write)
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val s0_addr = Cat(s0_acq.addr_block, s0_acq.addr_beat)
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val s1_addr_beat = s1_acq.addr_beat + Mux(io.grant.ready, UInt(1), UInt(0))
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val s1_addr = Cat(s1_acq.addr_block, s1_addr_beat)
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val raddr = Mux(state_getblk, s1_addr, s0_addr)
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val waddr = s0_addr
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val rdata = bram.read(raddr, ren)
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val wdata = s0_acq.data
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val wmask = s0_acq.wmask()
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when (wen) {
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bram.write(waddr, wdata)
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assert(wmask.andR, "BRAMSlave: partial write masks not supported")
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bram.write(acq_addr, io.acquire.bits.data)
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assert(io.acquire.bits.wmask().andR, "BRAMSlave: partial write masks not supported")
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}
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val stall = io.grant.valid && !io.grant.ready
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io.acquire.ready := state_init && !stall
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when (fire_acq) {
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state_getblk := is_getblk
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state_putblk := is_putblk && s0_last
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}
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when (state_getblk && fire_gnt) {
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s1_acq.addr_beat := s1_addr_beat
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state_getblk := !s1_last
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}
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when (state_putblk && fire_gnt) {
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state_putblk := Bool(false)
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}
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io.grant.valid := s1_valid
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = s1_acq.getBuiltInGrantType(),
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client_xact_id = s1_acq.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = s1_acq.addr_beat,
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data = rdata)
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io.grant.bits.data := RegEnable(bram.read(acq_addr), ren)
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}
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class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
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