riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Configs: add a parameter to control the memory subsystem interface

This commit is contained in:
Wesley W. Terpstra 2016-06-01 15:00:48 -07:00 committed by Andrew Waterman
parent 2ddada1732
commit 2086c0d603
2 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/main/scala/Configs.scala
View File

@ -296,6 +296,7 @@ class BaseConfig extends Config (
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case TMemoryChannels => BusType.AXI
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")
case NOutstandingMemReqsPerChannel => site(NBanksPerMemoryChannel)*(site(NAcquireTransactors)+2)
case BankIdLSB => 0

9
src/main/scala/RocketChip.scala
View File

@ -11,8 +11,17 @@ import rocket.Util._
/** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
/** Options for memory bus interface */
object BusType {
sealed trait EnumVal
case object AXI extends EnumVal
case object AHB extends EnumVal
val busTypes = Seq(AXI, AHB)
}
/** Number of memory channels */
case object NMemoryChannels extends Field[Int]
case object TMemoryChannels extends Field[BusType.EnumVal]
/** Number of banks per memory channel */
case object NBanksPerMemoryChannel extends Field[Int]
/** Least significant bit of address used for bank partitioning */