ext: support multiple external AHB/AXI ports
This commit is contained in:
Wesley W. Terpstra
parent
36720d915a
commit
8ac7fa5544
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@ -38,25 +38,10 @@ class BaseConfig extends Config (
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}
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = 0x80000000L
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val ioMap = ListBuffer(AddrMapEntry("int", internalIOAddrMap))
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val nMMIOChannels =
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site(NExtMMIOAXIChannels) +
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site(NExtMMIOAHBChannels) +
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site(NExtMMIOTLChannels)
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if (nMMIOChannels > 0) {
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val extIOBase = 0x60000000L
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val extIOSize = 0x20000000L
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ioMap += AddrMapEntry("ext", MemRange(extIOBase, extIOSize, MemAttr(AddrMapProt.RWX)))
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Dump("IO_BASE", extIOBase)
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Dump("IO_SIZE", extIOSize)
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}
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val memSize = 0x10000000L
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val io = AddrMap((AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries):_*)
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val addrMap = AddrMap(
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AddrMapEntry("io", new AddrMap(ioMap.toSeq)),
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AddrMapEntry("io", io),
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AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
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Dump("MEM_BASE", addrMap("mem").start)
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@ -231,6 +216,12 @@ class BaseConfig extends Config (
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true
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}
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case NExtInterrupts => 2
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case ExtMMIOPorts => AddrMap()
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/*
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AddrMap(
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AddrMapEntry("cfg", MemRange(0x50000000L, 0x04000000L, MemAttr(AddrMapProt.RW))),
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AddrMapEntry("ext", MemRange(0x60000000L, 0x20000000L, MemAttr(AddrMapProt.RWX))))
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*/
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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@ -35,6 +35,7 @@ case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Number of exteral MMIO ports */
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case object ExtMMIOPorts extends Field[AddrMap]
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case object NExtMMIOAXIChannels extends Field[Int]
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case object NExtMMIOAHBChannels extends Field[Int]
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case object NExtMMIOTLChannels extends Field[Int]
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@ -226,24 +227,27 @@ class Uncore(implicit val p: Parameters) extends Module
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io.mem_ahb <> outmemsys.io.mem_ahb
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io.mem_tl <> outmemsys.io.mem_tl
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def connectExternalMMIO(ext: ClientUncachedTileLinkIO)(implicit p: Parameters) {
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val mmio_axi = p(NExtMMIOAXIChannels)
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val mmio_ahb = p(NExtMMIOAHBChannels)
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val mmio_tl = p(NExtMMIOTLChannels)
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require (mmio_axi + mmio_ahb + mmio_tl <= 1)
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if (mmio_ahb == 1) {
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val ahb = Module(new AHBBridge(true)) // with atomics
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io.mmio_ahb.head <> ahb.io.ahb
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ahb.io.tl <> ext
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} else if (mmio_tl == 1) {
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TopUtils.connectTilelink(io.mmio_tl.head, ext)
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} else {
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val mmioEndpoint = mmio_axi match {
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case 0 => Module(new NastiErrorSlave).io
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case 1 => io.mmio_axi.head
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def connectExternalMMIO(ports: Seq[ClientUncachedTileLinkIO])(implicit p: Parameters) {
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val mmio_axi_start = 0
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val mmio_axi_end = mmio_axi_start + p(NExtMMIOAXIChannels)
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val mmio_ahb_start = mmio_axi_end
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val mmio_ahb_end = mmio_ahb_start + p(NExtMMIOAHBChannels)
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val mmio_tl_start = mmio_ahb_end
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val mmio_tl_end = mmio_tl_start + p(NExtMMIOTLChannels)
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require (mmio_tl_end == ports.size)
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for (i <- 0 until ports.size) {
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if (mmio_axi_start <= i && i < mmio_axi_end) {
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TopUtils.connectTilelinkNasti(io.mmio_axi(i-mmio_axi_start), ports(i))
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} else if (mmio_ahb_start <= i && i < mmio_ahb_end) {
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val ahbBridge = Module(new AHBBridge(true))
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io.mmio_ahb(i-mmio_ahb_start) <> ahbBridge.io.ahb
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ahbBridge.io.tl <> ports(i)
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} else if (mmio_tl_start <= i && i < mmio_tl_end) {
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TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i))
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} else {
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TopUtils.connectTilelinkNasti(Module(new NastiErrorSlave).io, ports(i))
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}
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TopUtils.connectTilelinkNasti(mmioEndpoint, ext)
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}
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}
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@ -282,23 +286,9 @@ class Uncore(implicit val p: Parameters) extends Module
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val bootROM = Module(new ROMSlave(TopUtils.makeBootROM()))
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bootROM.io <> mmioNetwork.port("int:bootrom")
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require(io.mmio_ahb.size + io.mmio_axi.size + io.mmio_tl.size <= 1,
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"Maximum of 1 external MMIO channel supported for now")
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io.mmio_ahb.foreach { ahb =>
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val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
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TopUtils.connectTilelinkAhb(ahb, ext)(outermostMMIOParams)
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}
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io.mmio_axi.foreach { axi =>
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val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
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TopUtils.connectTilelinkNasti(axi, ext)(outermostMMIOParams)
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}
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io.mmio_tl.foreach { tl =>
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val ext = TileLinkWidthAdapter(mmioNetwork.port("ext"), "MMIO_Outermost")
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TopUtils.connectTilelink(tl, ext)(outermostMMIOParams)
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}
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// The memory map presently has only one external I/O region
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val ext = p(ExtMMIOPorts).entries.map(port => TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost"))
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connectExternalMMIO(ext)(outermostMMIOParams)
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}
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}
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