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tilelink2: IDNode needs to be specialized for output vs. input passthrough

This commit is contained in:
Wesley W. Terpstra 2016-08-30 19:26:01 -07:00
parent eac4d44131
commit 5b31fb81fe
2 changed files with 33 additions and 9 deletions

View File

@ -29,12 +29,14 @@ abstract class TLFactory
}
}
bindings.foreach { case (x, i, y, j, s) =>
TLMonitor.legalize(y.bundleOut(j), y.edgesOut(j), x.bundleIn(i), x.edgesIn(i), s)
x.bundleIn(i).<>(y.bundleOut(j))(s)
val in = x.connectIn(i)
val out = y.connectOut(j)
TLMonitor.legalize(out, y.edgesOut(j), in, x.edgesIn(i), s)
in.<>(out)(s)
val mask = ~UInt(x.edgesIn(i).manager.beatBytes - 1)
x.bundleIn (i).a.bits.address.:=(mask & y.bundleOut(j).a.bits.address)(s)
y.bundleOut(j).b.bits.address.:=(mask & x.bundleIn (i).b.bits.address)(s)
x.bundleIn (i).c.bits.address.:=(mask & y.bundleOut(j).c.bits.address)(s)
in .a.bits.address.:=(mask & out.a.bits.address)(s)
out.b.bits.address.:=(mask & in .b.bits.address)(s)
in .c.bits.address.:=(mask & out.c.bits.address)(s)
}
}
}

View File

@ -50,6 +50,9 @@ class TLBaseNode(
lazy val bundleOut = { require (!edgesOut.isEmpty); Vec(edgesOut.size, TLBundle(edgesOut.map(_.bundle).reduce(_.union(_)))) }
lazy val bundleIn = { require (!edgesIn .isEmpty); Vec(edgesIn .size, TLBundle(edgesIn .map(_.bundle).reduce(_.union(_)))).flip }
def connectOut = bundleOut
def connectIn = bundleIn
}
class TLClientNode(
@ -109,13 +112,32 @@ object TLAdapterNode
numManagerPorts: Range.Inclusive = 1 to 1) = new TLAdapterNode(clientFn, managerFn, numClientPorts, numManagerPorts)
}
class TLIDNode extends TLBaseNode(
class TLOutputNode extends TLBaseNode(
clientFn = Some({case Seq(x) => x}),
managerFn = Some({case Seq(x) => x}),
numClientPorts = 1 to 1,
numManagerPorts = 1 to 1)
object TLIDNode
{
def apply() = new TLIDNode()
override def connectOut = bundleOut
override def connectIn = bundleOut
}
object TLOutputNode
{
def apply() = new TLOutputNode()
}
class TLInputNode extends TLBaseNode(
clientFn = Some({case Seq(x) => x}),
managerFn = Some({case Seq(x) => x}),
numClientPorts = 1 to 1,
numManagerPorts = 1 to 1)
{
override def connectOut = bundleIn
override def connectIn = bundleIn
}
object TLInputNode
{
def apply() = new TLInputNode()
}