tilelink2: IDNode needs to be specialized for output vs. input passthrough
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@ -29,12 +29,14 @@ abstract class TLFactory
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}
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}
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bindings.foreach { case (x, i, y, j, s) =>
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TLMonitor.legalize(y.bundleOut(j), y.edgesOut(j), x.bundleIn(i), x.edgesIn(i), s)
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x.bundleIn(i).<>(y.bundleOut(j))(s)
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val in = x.connectIn(i)
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val out = y.connectOut(j)
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TLMonitor.legalize(out, y.edgesOut(j), in, x.edgesIn(i), s)
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in.<>(out)(s)
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val mask = ~UInt(x.edgesIn(i).manager.beatBytes - 1)
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x.bundleIn (i).a.bits.address.:=(mask & y.bundleOut(j).a.bits.address)(s)
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y.bundleOut(j).b.bits.address.:=(mask & x.bundleIn (i).b.bits.address)(s)
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x.bundleIn (i).c.bits.address.:=(mask & y.bundleOut(j).c.bits.address)(s)
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in .a.bits.address.:=(mask & out.a.bits.address)(s)
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out.b.bits.address.:=(mask & in .b.bits.address)(s)
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in .c.bits.address.:=(mask & out.c.bits.address)(s)
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}
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}
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}
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@ -50,6 +50,9 @@ class TLBaseNode(
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lazy val bundleOut = { require (!edgesOut.isEmpty); Vec(edgesOut.size, TLBundle(edgesOut.map(_.bundle).reduce(_.union(_)))) }
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lazy val bundleIn = { require (!edgesIn .isEmpty); Vec(edgesIn .size, TLBundle(edgesIn .map(_.bundle).reduce(_.union(_)))).flip }
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def connectOut = bundleOut
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def connectIn = bundleIn
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}
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class TLClientNode(
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@ -109,13 +112,32 @@ object TLAdapterNode
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numManagerPorts: Range.Inclusive = 1 to 1) = new TLAdapterNode(clientFn, managerFn, numClientPorts, numManagerPorts)
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}
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class TLIDNode extends TLBaseNode(
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class TLOutputNode extends TLBaseNode(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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numManagerPorts = 1 to 1)
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object TLIDNode
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{
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def apply() = new TLIDNode()
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override def connectOut = bundleOut
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override def connectIn = bundleOut
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}
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object TLOutputNode
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{
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def apply() = new TLOutputNode()
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}
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class TLInputNode extends TLBaseNode(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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numManagerPorts = 1 to 1)
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{
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override def connectOut = bundleIn
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override def connectIn = bundleIn
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}
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object TLInputNode
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{
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def apply() = new TLInputNode()
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}
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