tilelink2: mask out unnecessary address bits
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@ -31,6 +31,10 @@ abstract class TLFactory
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bindings.foreach { case (x, i, y, j, s) =>
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TLMonitor.legalize(y.bundleOut(j), y.edgesOut(j), x.bundleIn(i), x.edgesIn(i), s)
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x.bundleIn(i).<>(y.bundleOut(j))(s)
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val mask = ~UInt(x.edgesIn(i).manager.beatBytes - 1)
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x.bundleIn (i).a.bits.address.:=(mask & y.bundleOut(j).a.bits.address)(s)
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y.bundleOut(j).b.bits.address.:=(mask & x.bundleIn (i).b.bits.address)(s)
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x.bundleIn (i).c.bits.address.:=(mask & y.bundleOut(j).c.bits.address)(s)
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}
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}
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}
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