tilelink2: add an intermediate type for simple factories
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@ -39,6 +39,12 @@ abstract class TLFactory
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}
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}
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// Use this if you have only one node => makes factory adapters possible
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abstract class TLSimpleFactory extends TLFactory
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{
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def node: TLBaseNode
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}
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abstract class TLModule(factory: TLFactory) extends Module
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{
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override def desiredName = factory.getClass.getName.split('.').last
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@ -59,7 +59,7 @@ object TLRegisterNode
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// register mapped device from a totally abstract register mapped device.
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// See GPIO.scala in this directory for an example
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abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLFactory
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abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLSimpleFactory
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{
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val node = TLRegisterNode(address, concurrency, beatBytes)
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}
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@ -4,7 +4,7 @@ package uncore.tilelink2
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import Chisel._
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLFactory
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
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{
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val node = TLManagerNode(beatBytes, TLManagerParameters(
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address = List(address),
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@ -13,7 +13,7 @@ object TLXbar
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}
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}
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class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLFactory
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class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLSimpleFactory
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{
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def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
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def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
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